target/riscv: Sign extend link reg for jal and jalr
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-4-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -68,9 +68,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
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tcg_temp_free(t0);
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tcg_temp_free(t0);
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}
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}
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if (a->rd != 0) {
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gen_set_gpri(ctx, a->rd, ctx->pc_succ_insn);
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tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
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}
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tcg_gen_lookup_and_goto_ptr();
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tcg_gen_lookup_and_goto_ptr();
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if (misaligned) {
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if (misaligned) {
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@ -369,10 +369,8 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
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return;
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return;
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}
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}
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}
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}
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if (rd != 0) {
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tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
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}
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gen_set_gpri(ctx, rd, ctx->pc_succ_insn);
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gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */
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gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */
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ctx->base.is_jmp = DISAS_NORETURN;
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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}
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