target-arm queue:
* Fix calculation of ICH_MISR_EL2.LRENP to avoid incorrect generation of maintenance interrupts -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmGvl3oZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3v7QEACV56kO/+fNnQnfmxYZL+8V bICn6UWpioQk7vw0Btx6IkdziKJFAwb6fWY/tRPsUalwhmLX9b1EhwnvyUosnNfe 1TfKdByB5IJY/Jbul5rCKM5N68k+sySns+j840/XtFummKnGYvJ3vzq7D1eW7tKA tQjpkMC7NcOgSHG4aIprC7kW0XUzE4TGXuDci+Cit8sMwCVE98J78LrhxCcpo4u2 bSEkvPtHJpP0/tiB/TesXUOlP7srhg1iBlk+j+ffkKHcCcX9bEUrOLCF6r2fHsjo MYX+mOtSGhcc0Vp4+7tJ2/h6at2DfAF7JWxilKBJoTGXnj4XEapIXIaPJP5niTyC z+JGiyVD8IkR27HJ8GDk8dkGn98MgtB6iMqBL61eNpPq6SH5eM5w/ys5WYVW7sHK 6wJ+K/ecTWxAm4ykknO17dCYtGXyLko/+5xua2XcDZvdlxSxCXr8g89feXbD5eki MnfhhblVQ/DsZdDieL0fykNsVqhae6U9IK6YwvZxm1mlJVkF2dnwV6+UdenAyMi0 TGphr2pR8u+/vnG1UKOnD9YLf1gikhrmarM5vl2Jb4/eLHFwhEkAuW5immBuHb4Y pcijbEH3gQQBd843Hv8e8ogBj73Y/k56qTgbDSvvlS2cYCsCa0g0Manm0cDxaInF 43nubUH2syrRyAEUMQSecA== =4xrR -----END PGP SIGNATURE----- Merge tag 'pull-target-arm-20211207' of https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Fix calculation of ICH_MISR_EL2.LRENP to avoid incorrect generation of maintenance interrupts # gpg: Signature made Tue 07 Dec 2021 09:18:50 AM PST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] * tag 'pull-target-arm-20211207' of https://git.linaro.org/people/pmaydell/qemu-arm: gicv3: fix ICH_MISR's LRENP computation Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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commit
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@ -351,7 +351,8 @@ static uint32_t maintenance_interrupt_state(GICv3CPUState *cs)
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/* Scan list registers and fill in the U, NP and EOI bits */
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/* Scan list registers and fill in the U, NP and EOI bits */
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eoi_maintenance_interrupt_state(cs, &value);
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eoi_maintenance_interrupt_state(cs, &value);
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if (cs->ich_hcr_el2 & (ICH_HCR_EL2_LRENPIE | ICH_HCR_EL2_EOICOUNT_MASK)) {
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if ((cs->ich_hcr_el2 & ICH_HCR_EL2_LRENPIE) &&
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(cs->ich_hcr_el2 & ICH_HCR_EL2_EOICOUNT_MASK)) {
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value |= ICH_MISR_EL2_LRENP;
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value |= ICH_MISR_EL2_LRENP;
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}
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}
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