pcnet-pci: mark I/O and MMIO as LITTLE_ENDIAN
Now that the memory subsystem is propagating the endianness correctly, the pcnet-pci device should have its I/O ports and MMIO memory marked as LITTLE_ENDIAN, as PCI devices are little endian. This makes the pcnet-pci NIC to work again on big endian MIPS Malta (default NIC). Cc: qemu-stable@nongnu.org Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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@ -134,7 +134,7 @@ static void pcnet_ioport_write(void *opaque, hwaddr addr,
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static const MemoryRegionOps pcnet_io_ops = {
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static const MemoryRegionOps pcnet_io_ops = {
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.read = pcnet_ioport_read,
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.read = pcnet_ioport_read,
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.write = pcnet_ioport_write,
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.write = pcnet_ioport_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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};
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static void pcnet_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
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static void pcnet_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
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@ -256,7 +256,7 @@ static const MemoryRegionOps pcnet_mmio_ops = {
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.read = { pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl },
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.read = { pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl },
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.write = { pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel },
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.write = { pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel },
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},
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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};
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static void pci_physical_memory_write(void *dma_opaque, hwaddr addr,
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static void pci_physical_memory_write(void *dma_opaque, hwaddr addr,
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