target/riscv: Extend the SIP CSR to support virtulisation
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
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@ -743,8 +743,19 @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
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static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
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static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
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target_ulong new_value, target_ulong write_mask)
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target_ulong new_value, target_ulong write_mask)
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{
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{
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int ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
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int ret;
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if (riscv_cpu_virt_enabled(env)) {
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/* Shift the new values to line up with the VS bits */
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ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
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(write_mask & sip_writable_mask) << 1 & env->mideleg);
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ret &= vsip_writable_mask;
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ret >>= 1;
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} else {
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ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
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write_mask & env->mideleg & sip_writable_mask);
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write_mask & env->mideleg & sip_writable_mask);
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}
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*ret_value &= env->mideleg;
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*ret_value &= env->mideleg;
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return ret;
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return ret;
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}
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}
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