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target/mips: Clean up handling of CP0 register 28

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Clean up handling of CP0 register 28.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-28-git-send-email-aleksandar.markovic@rt-rk.com>
This commit is contained in:
Aleksandar Markovic 2019-08-28 18:26:51 +02:00
parent 5a10873d7d
commit a30e2f2180
2 changed files with 46 additions and 42 deletions
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24
target/mips/cpu.h
View file

@ -233,12 +233,12 @@ typedef struct mips_def_t mips_def_t;
*
* 0 DataLo DataHi ErrorEPC DESAVE
* 1 TagLo TagHi
* 2 DataLo DataHi KScratch<n>
* 3 TagLo TagHi KScratch<n>
* 4 DataLo DataHi KScratch<n>
* 5 TagLo TagHi KScratch<n>
* 6 DataLo DataHi KScratch<n>
* 7 TagLo TagHi KScratch<n>
* 2 DataLo1 DataHi KScratch<n>
* 3 TagLo1 TagHi KScratch<n>
* 4 DataLo2 DataHi KScratch<n>
* 5 TagLo2 TagHi KScratch<n>
* 6 DataLo3 DataHi KScratch<n>
* 7 TagLo3 TagHi KScratch<n>
*
*/
#define CP0_REGISTER_00 0
@ -427,10 +427,14 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 27 */
#define CP0_REG27__CACHERR 0
/* CP0 Register 28 */
#define CP0_REG28__ITAGLO 0
#define CP0_REG28__IDATALO 1
#define CP0_REG28__DTAGLO 2
#define CP0_REG28__DDATALO 3
#define CP0_REG28__TAGLO 0
#define CP0_REG28__DATALO 1
#define CP0_REG28__TAGLO1 2
#define CP0_REG28__DATALO1 3
#define CP0_REG28__TAGLO2 4
#define CP0_REG28__DATALO2 5
#define CP0_REG28__TAGLO3 6
#define CP0_REG28__DATALO3 7
/* CP0 Register 29 */
#define CP0_REG29__IDATAHI 1
#define CP0_REG29__DDATAHI 3

64
target/mips/translate.c
View file

@ -7476,10 +7476,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_28:
switch (sel) {
case 0:
case 2:
case 4:
case 6:
case CP0_REG28__TAGLO:
case CP0_REG28__TAGLO1:
case CP0_REG28__TAGLO2:
case CP0_REG28__TAGLO3:
{
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUMIPSState, CP0_TagLo));
@ -7488,10 +7488,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
}
register_name = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
case CP0_REG28__DATALO:
case CP0_REG28__DATALO1:
case CP0_REG28__DATALO2:
case CP0_REG28__DATALO3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
register_name = "DataLo";
break;
@ -8231,17 +8231,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_28:
switch (sel) {
case 0:
case 2:
case 4:
case 6:
case CP0_REG28__TAGLO:
case CP0_REG28__TAGLO1:
case CP0_REG28__TAGLO2:
case CP0_REG28__TAGLO3:
gen_helper_mtc0_taglo(cpu_env, arg);
register_name = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
case CP0_REG28__DATALO:
case CP0_REG28__DATALO1:
case CP0_REG28__DATALO2:
case CP0_REG28__DATALO3:
gen_helper_mtc0_datalo(cpu_env, arg);
register_name = "DataLo";
break;
@ -8959,17 +8959,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_28:
switch (sel) {
case 0:
case 2:
case 4:
case 6:
case CP0_REG28__TAGLO:
case CP0_REG28__TAGLO1:
case CP0_REG28__TAGLO2:
case CP0_REG28__TAGLO3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagLo));
register_name = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
case CP0_REG28__DATALO:
case CP0_REG28__DATALO1:
case CP0_REG28__DATALO2:
case CP0_REG28__DATALO3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
register_name = "DataLo";
break;
@ -9695,17 +9695,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_28:
switch (sel) {
case 0:
case 2:
case 4:
case 6:
case CP0_REG28__TAGLO:
case CP0_REG28__TAGLO1:
case CP0_REG28__TAGLO2:
case CP0_REG28__TAGLO3:
gen_helper_mtc0_taglo(cpu_env, arg);
register_name = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
case CP0_REG28__DATALO:
case CP0_REG28__DATALO1:
case CP0_REG28__DATALO2:
case CP0_REG28__DATALO3:
gen_helper_mtc0_datalo(cpu_env, arg);
register_name = "DataLo";
break;