Three patches to fix ExtINT for the QEMU implementation of the local APIC.
-----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQEcBAABAgAGBQJUczTcAAoJEL/70l94x66D/dEIAKMy5aOkmcPHcptzpK77LBJC H6FuYmdUOvLlzrPPV9DeWmFQDN8i1ySvJKRQ0F1KKAE9hm4vKl/w6cibY3abI/VB xu/c7o8XTeLt5f+3OFeqSvRX1Wx/3Fj+v0lauHzAjyVZxd3mQ1wOxygzQtSkoJPq akJEgb0jURN8MfiqwMl1ws1iSdRhPE4pR/q63GgOCNZFF9O0ADZueO+SNztBxTTp t2xYiNqjeG+b+AKrn0bkFdAQvLD4jzBIyOmQClwdQsd6Qwc88/246FJD6OdBwBBW Zp3HAeLuxvw8aWGfs+x4FRLDAeOJ+BPfwlyJJiyb9DuzpA/ayL0qQfWXcX9pY3g= =8ow4 -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging Three patches to fix ExtINT for the QEMU implementation of the local APIC. # gpg: Signature made Mon 24 Nov 2014 13:38:36 GMT using RSA key ID 78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: apic: fix incorrect handling of ExtINT interrupts wrt processor priority apic: fix loss of IPI due to masked ExtINT apic: avoid getting out of halted state on masked PIC interrupts Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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a31a7475e9
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@ -188,7 +188,7 @@ void apic_deliver_pic_intr(DeviceState *dev, int level)
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apic_reset_bit(s->irr, lvt & 0xff);
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/* fall through */
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case APIC_DM_EXTINT:
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cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD);
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apic_update_irq(s);
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break;
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}
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}
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@ -349,6 +349,11 @@ static int apic_get_arb_pri(APICCommonState *s)
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static int apic_irq_pending(APICCommonState *s)
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{
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int irrv, ppr;
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if (!(s->spurious_vec & APIC_SV_ENABLE)) {
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return 0;
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}
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irrv = get_highest_priority_int(s->irr);
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if (irrv < 0) {
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return 0;
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@ -366,14 +371,13 @@ static void apic_update_irq(APICCommonState *s)
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{
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CPUState *cpu;
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if (!(s->spurious_vec & APIC_SV_ENABLE)) {
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return;
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}
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cpu = CPU(s->cpu);
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if (!qemu_cpu_is_self(cpu)) {
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cpu_interrupt(cpu, CPU_INTERRUPT_POLL);
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} else if (apic_irq_pending(s) > 0) {
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cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
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} else if (!apic_accept_pic_intr(&s->busdev.qdev) || !pic_get_output(isa_pic)) {
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cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);
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}
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}
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@ -567,7 +571,10 @@ int apic_get_interrupt(DeviceState *dev)
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apic_sync_vapic(s, SYNC_FROM_VAPIC);
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intno = apic_irq_pending(s);
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if (intno == 0) {
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/* if there is an interrupt from the 8259, let the caller handle
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* that first since ExtINT interrupts ignore the priority.
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*/
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if (intno == 0 || apic_check_pic(s)) {
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apic_sync_vapic(s, SYNC_TO_VAPIC);
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return -1;
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} else if (intno < 0) {
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@ -578,9 +585,6 @@ int apic_get_interrupt(DeviceState *dev)
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apic_set_bit(s->isr, intno);
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apic_sync_vapic(s, SYNC_TO_VAPIC);
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/* re-inject if there is still a pending PIC interrupt */
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apic_check_pic(s);
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apic_update_irq(s);
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return intno;
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@ -2912,8 +2912,14 @@ static bool x86_cpu_has_work(CPUState *cs)
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
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CPU_INTERRUPT_POLL)) &&
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#if !defined(CONFIG_USER_ONLY)
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if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
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apic_poll_irq(cpu->apic_state);
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cpu_reset_interrupt(cs, CPU_INTERRUPT_POLL);
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}
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#endif
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return ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
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(env->eflags & IF_MASK)) ||
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(cs->interrupt_request & (CPU_INTERRUPT_NMI |
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CPU_INTERRUPT_INIT |
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