hw/pl061: Convert to VMState
Convert the PL061 to VMState. We choose to widen the struct members to uint32_t rather than the other two options of breaking migration compatibility or using vmstate hacks to read/write a 32 bit value into an 8 bit struct field. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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174
hw/pl061.c
174
hw/pl061.c
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@ -30,31 +30,60 @@ static const uint8_t pl061_id_luminary[12] =
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typedef struct {
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SysBusDevice busdev;
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int locked;
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uint8_t data;
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uint8_t old_data;
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uint8_t dir;
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uint8_t isense;
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uint8_t ibe;
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uint8_t iev;
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uint8_t im;
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uint8_t istate;
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uint8_t afsel;
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uint8_t dr2r;
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uint8_t dr4r;
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uint8_t dr8r;
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uint8_t odr;
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uint8_t pur;
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uint8_t pdr;
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uint8_t slr;
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uint8_t den;
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uint8_t cr;
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uint8_t float_high;
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uint32_t locked;
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uint32_t data;
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uint32_t old_data;
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uint32_t dir;
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uint32_t isense;
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uint32_t ibe;
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uint32_t iev;
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uint32_t im;
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uint32_t istate;
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uint32_t afsel;
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uint32_t dr2r;
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uint32_t dr4r;
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uint32_t dr8r;
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uint32_t odr;
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uint32_t pur;
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uint32_t pdr;
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uint32_t slr;
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uint32_t den;
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uint32_t cr;
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uint32_t float_high;
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qemu_irq irq;
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qemu_irq out[8];
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const unsigned char *id;
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} pl061_state;
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static const VMStateDescription vmstate_pl061 = {
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.name = "pl061",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(locked, pl061_state),
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VMSTATE_UINT32(data, pl061_state),
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VMSTATE_UINT32(old_data, pl061_state),
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VMSTATE_UINT32(dir, pl061_state),
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VMSTATE_UINT32(isense, pl061_state),
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VMSTATE_UINT32(ibe, pl061_state),
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VMSTATE_UINT32(iev, pl061_state),
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VMSTATE_UINT32(im, pl061_state),
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VMSTATE_UINT32(istate, pl061_state),
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VMSTATE_UINT32(afsel, pl061_state),
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VMSTATE_UINT32(dr2r, pl061_state),
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VMSTATE_UINT32(dr4r, pl061_state),
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VMSTATE_UINT32(dr8r, pl061_state),
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VMSTATE_UINT32(odr, pl061_state),
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VMSTATE_UINT32(pur, pl061_state),
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VMSTATE_UINT32(pdr, pl061_state),
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VMSTATE_UINT32(slr, pl061_state),
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VMSTATE_UINT32(den, pl061_state),
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VMSTATE_UINT32(cr, pl061_state),
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VMSTATE_UINT32(float_high, pl061_state),
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VMSTATE_END_OF_LIST()
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}
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};
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static void pl061_update(pl061_state *s)
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{
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uint8_t changed;
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@ -148,19 +177,19 @@ static void pl061_write(void *opaque, target_phys_addr_t offset,
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}
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switch (offset) {
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case 0x400: /* Direction */
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s->dir = value;
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s->dir = value & 0xff;
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break;
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case 0x404: /* Interrupt sense */
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s->isense = value;
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s->isense = value & 0xff;
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break;
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case 0x408: /* Interrupt both edges */
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s->ibe = value;
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s->ibe = value & 0xff;
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break;
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case 0x40c: /* Interrupt event */
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s->iev = value;
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s->iev = value & 0xff;
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break;
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case 0x410: /* Interrupt mask */
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s->im = value;
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s->im = value & 0xff;
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break;
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case 0x41c: /* Interrupt clear */
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s->istate &= ~value;
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@ -170,35 +199,35 @@ static void pl061_write(void *opaque, target_phys_addr_t offset,
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s->afsel = (s->afsel & ~mask) | (value & mask);
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break;
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case 0x500: /* 2mA drive */
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s->dr2r = value;
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s->dr2r = value & 0xff;
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break;
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case 0x504: /* 4mA drive */
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s->dr4r = value;
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s->dr4r = value & 0xff;
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break;
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case 0x508: /* 8mA drive */
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s->dr8r = value;
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s->dr8r = value & 0xff;
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break;
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case 0x50c: /* Open drain */
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s->odr = value;
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s->odr = value & 0xff;
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break;
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case 0x510: /* Pull-up */
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s->pur = value;
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s->pur = value & 0xff;
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break;
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case 0x514: /* Pull-down */
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s->pdr = value;
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s->pdr = value & 0xff;
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break;
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case 0x518: /* Slew rate control */
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s->slr = value;
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s->slr = value & 0xff;
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break;
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case 0x51c: /* Digital enable */
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s->den = value;
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s->den = value & 0xff;
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break;
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case 0x520: /* Lock */
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s->locked = (value != 0xacce551);
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break;
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case 0x524: /* Commit */
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if (!s->locked)
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s->cr = value;
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s->cr = value & 0xff;
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break;
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default:
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hw_error("pl061_write: Bad offset %x\n", (int)offset);
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@ -238,62 +267,6 @@ static CPUWriteMemoryFunc * const pl061_writefn[] = {
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pl061_write
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};
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static void pl061_save(QEMUFile *f, void *opaque)
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{
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pl061_state *s = (pl061_state *)opaque;
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qemu_put_be32(f, s->locked);
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qemu_put_be32(f, s->data);
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qemu_put_be32(f, s->old_data);
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qemu_put_be32(f, s->dir);
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qemu_put_be32(f, s->isense);
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qemu_put_be32(f, s->ibe);
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qemu_put_be32(f, s->iev);
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qemu_put_be32(f, s->im);
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qemu_put_be32(f, s->istate);
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qemu_put_be32(f, s->afsel);
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qemu_put_be32(f, s->dr2r);
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qemu_put_be32(f, s->dr4r);
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qemu_put_be32(f, s->dr8r);
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qemu_put_be32(f, s->odr);
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qemu_put_be32(f, s->pur);
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qemu_put_be32(f, s->pdr);
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qemu_put_be32(f, s->slr);
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qemu_put_be32(f, s->den);
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qemu_put_be32(f, s->cr);
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qemu_put_be32(f, s->float_high);
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}
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static int pl061_load(QEMUFile *f, void *opaque, int version_id)
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{
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pl061_state *s = (pl061_state *)opaque;
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if (version_id != 1)
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return -EINVAL;
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s->locked = qemu_get_be32(f);
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s->data = qemu_get_be32(f);
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s->old_data = qemu_get_be32(f);
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s->dir = qemu_get_be32(f);
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s->isense = qemu_get_be32(f);
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s->ibe = qemu_get_be32(f);
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s->iev = qemu_get_be32(f);
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s->im = qemu_get_be32(f);
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s->istate = qemu_get_be32(f);
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s->afsel = qemu_get_be32(f);
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s->dr2r = qemu_get_be32(f);
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s->dr4r = qemu_get_be32(f);
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s->dr8r = qemu_get_be32(f);
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s->odr = qemu_get_be32(f);
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s->pur = qemu_get_be32(f);
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s->pdr = qemu_get_be32(f);
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s->slr = qemu_get_be32(f);
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s->den = qemu_get_be32(f);
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s->cr = qemu_get_be32(f);
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s->float_high = qemu_get_be32(f);
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return 0;
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}
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static int pl061_init(SysBusDevice *dev, const unsigned char *id)
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{
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int iomemtype;
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@ -307,7 +280,6 @@ static int pl061_init(SysBusDevice *dev, const unsigned char *id)
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qdev_init_gpio_in(&dev->qdev, pl061_set_irq, 8);
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qdev_init_gpio_out(&dev->qdev, s->out, 8);
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pl061_reset(s);
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register_savevm(&dev->qdev, "pl061_gpio", -1, 1, pl061_save, pl061_load, s);
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return 0;
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}
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@ -321,12 +293,24 @@ static int pl061_init_arm(SysBusDevice *dev)
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return pl061_init(dev, pl061_id);
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}
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static SysBusDeviceInfo pl061_info = {
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.init = pl061_init_arm,
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.qdev.name = "pl061",
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.qdev.size = sizeof(pl061_state),
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.qdev.vmsd = &vmstate_pl061,
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};
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static SysBusDeviceInfo pl061_luminary_info = {
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.init = pl061_init_luminary,
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.qdev.name = "pl061_luminary",
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.qdev.size = sizeof(pl061_state),
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.qdev.vmsd = &vmstate_pl061,
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};
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static void pl061_register_devices(void)
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{
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sysbus_register_dev("pl061", sizeof(pl061_state),
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pl061_init_arm);
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sysbus_register_dev("pl061_luminary", sizeof(pl061_state),
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pl061_init_luminary);
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sysbus_register_withprop(&pl061_info);
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sysbus_register_withprop(&pl061_luminary_info);
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}
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device_init(pl061_register_devices)
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