dma/rc4030: create custom DMA address space
Add a new memory region in system address space where DMA address space definition (the 'translation table') belongs, so we can update on the fly the DMA address space. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
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163
hw/dma/rc4030.c
163
hw/dma/rc4030.c
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@ -25,6 +25,7 @@
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#include "hw/hw.h"
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#include "hw/mips/mips.h"
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#include "qemu/timer.h"
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#include "exec/address-spaces.h"
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/********************************************************/
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/* debug rc4030 */
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@ -47,6 +48,8 @@ do { fprintf(stderr, "rc4030 ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } whi
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/********************************************************/
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/* rc4030 emulation */
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#define MAX_TL_ENTRIES 512
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typedef struct dma_pagetable_entry {
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int32_t frame;
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int32_t owner;
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@ -96,6 +99,16 @@ typedef struct rc4030State
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qemu_irq timer_irq;
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qemu_irq jazz_bus_irq;
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/* biggest translation table */
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MemoryRegion dma_tt;
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/* translation table memory region alias, added to system RAM */
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MemoryRegion dma_tt_alias;
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/* whole DMA memory region, root of DMA address space */
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MemoryRegion dma_mr;
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/* translation table entry aliases, added to DMA memory region */
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MemoryRegion dma_mrs[MAX_TL_ENTRIES];
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AddressSpace dma_as;
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MemoryRegion iomem_chipset;
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MemoryRegion iomem_jazzio;
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} rc4030State;
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@ -265,6 +278,97 @@ static uint32_t rc4030_readb(void *opaque, hwaddr addr)
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return (v >> (8 * (addr & 0x3))) & 0xff;
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}
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static void rc4030_dma_as_update_one(rc4030State *s, int index, uint32_t frame)
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{
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if (index < MAX_TL_ENTRIES) {
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memory_region_set_enabled(&s->dma_mrs[index], false);
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}
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if (!frame) {
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return;
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}
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if (index >= MAX_TL_ENTRIES) {
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qemu_log_mask(LOG_UNIMP,
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"rc4030: trying to use too high "
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"translation table entry %d (max allowed=%d)",
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index, MAX_TL_ENTRIES);
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return;
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}
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memory_region_set_alias_offset(&s->dma_mrs[index], frame);
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memory_region_set_enabled(&s->dma_mrs[index], true);
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}
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static void rc4030_dma_tt_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned int size)
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{
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rc4030State *s = opaque;
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/* write memory */
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memcpy(memory_region_get_ram_ptr(&s->dma_tt) + addr, &data, size);
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/* update dma address space (only if frame field has been written) */
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if (addr % sizeof(dma_pagetable_entry) == 0) {
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int index = addr / sizeof(dma_pagetable_entry);
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memory_region_transaction_begin();
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rc4030_dma_as_update_one(s, index, (uint32_t)data);
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memory_region_transaction_commit();
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}
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}
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static const MemoryRegionOps rc4030_dma_tt_ops = {
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.write = rc4030_dma_tt_write,
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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};
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static void rc4030_dma_tt_update(rc4030State *s, uint32_t new_tl_base,
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uint32_t new_tl_limit)
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{
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int entries, i;
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dma_pagetable_entry *dma_tl_contents;
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if (s->dma_tl_limit) {
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/* write old dma tl table to physical memory */
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memory_region_del_subregion(get_system_memory(), &s->dma_tt_alias);
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cpu_physical_memory_write(s->dma_tl_limit & 0x7fffffff,
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memory_region_get_ram_ptr(&s->dma_tt),
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memory_region_size(&s->dma_tt_alias));
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}
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object_unparent(OBJECT(&s->dma_tt_alias));
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s->dma_tl_base = new_tl_base;
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s->dma_tl_limit = new_tl_limit;
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new_tl_base &= 0x7fffffff;
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if (s->dma_tl_limit) {
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uint64_t dma_tt_size;
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if (s->dma_tl_limit <= memory_region_size(&s->dma_tt)) {
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dma_tt_size = s->dma_tl_limit;
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} else {
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dma_tt_size = memory_region_size(&s->dma_tt);
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}
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memory_region_init_alias(&s->dma_tt_alias, NULL,
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"dma-table-alias",
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&s->dma_tt, 0, dma_tt_size);
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dma_tl_contents = memory_region_get_ram_ptr(&s->dma_tt);
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cpu_physical_memory_read(new_tl_base, dma_tl_contents, dma_tt_size);
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memory_region_transaction_begin();
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entries = dma_tt_size / sizeof(dma_pagetable_entry);
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for (i = 0; i < entries; i++) {
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rc4030_dma_as_update_one(s, i, dma_tl_contents[i].frame);
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}
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memory_region_add_subregion(get_system_memory(), new_tl_base,
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&s->dma_tt_alias);
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memory_region_transaction_commit();
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} else {
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memory_region_init(&s->dma_tt_alias, NULL,
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"dma-table-alias", 0);
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}
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}
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static void rc4030_writel(void *opaque, hwaddr addr, uint32_t val)
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{
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rc4030State *s = opaque;
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@ -279,11 +383,11 @@ static void rc4030_writel(void *opaque, hwaddr addr, uint32_t val)
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break;
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/* DMA transl. table base */
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case 0x0018:
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s->dma_tl_base = val;
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rc4030_dma_tt_update(s, val, s->dma_tl_limit);
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break;
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/* DMA transl. table limit */
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case 0x0020:
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s->dma_tl_limit = val;
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rc4030_dma_tt_update(s, s->dma_tl_base, val);
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break;
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/* DMA transl. table invalidated */
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case 0x0028:
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@ -590,7 +694,7 @@ static void rc4030_reset(void *opaque)
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s->invalid_address_register = 0;
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memset(s->dma_regs, 0, sizeof(s->dma_regs));
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s->dma_tl_base = s->dma_tl_limit = 0;
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rc4030_dma_tt_update(s, 0, 0);
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s->remote_failed_address = s->memory_failed_address = 0;
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s->cache_maint = 0;
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@ -675,39 +779,8 @@ static void rc4030_save(QEMUFile *f, void *opaque)
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void rc4030_dma_memory_rw(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write)
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{
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rc4030State *s = opaque;
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hwaddr entry_addr;
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hwaddr phys_addr;
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dma_pagetable_entry entry;
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int index;
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int ncpy, i;
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i = 0;
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for (;;) {
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if (i == len) {
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break;
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}
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ncpy = DMA_PAGESIZE - (addr & (DMA_PAGESIZE - 1));
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if (ncpy > len - i)
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ncpy = len - i;
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/* Get DMA translation table entry */
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index = addr / DMA_PAGESIZE;
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if (index >= s->dma_tl_limit / sizeof(dma_pagetable_entry)) {
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break;
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}
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entry_addr = s->dma_tl_base + index * sizeof(dma_pagetable_entry);
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/* XXX: not sure. should we really use only lowest bits? */
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entry_addr &= 0x7fffffff;
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cpu_physical_memory_read(entry_addr, &entry, sizeof(entry));
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/* Read/write data at right place */
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phys_addr = entry.frame + (addr & (DMA_PAGESIZE - 1));
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cpu_physical_memory_rw(phys_addr, &buf[i], ncpy, is_write);
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i += ncpy;
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addr += ncpy;
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}
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address_space_rw(&s->dma_as, addr, MEMTXATTRS_UNSPECIFIED, buf, len,
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is_write);
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}
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static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write)
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@ -733,7 +806,8 @@ static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_wri
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dma_addr = s->dma_regs[n][DMA_REG_ADDRESS];
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/* Read/write data at right place */
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rc4030_dma_memory_rw(opaque, dma_addr, buf, len, is_write);
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address_space_rw(&s->dma_as, dma_addr, MEMTXATTRS_UNSPECIFIED,
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buf, len, is_write);
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s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR;
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s->dma_regs[n][DMA_REG_COUNT] -= len;
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@ -800,6 +874,7 @@ void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
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MemoryRegion *sysmem)
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{
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rc4030State *s;
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int i;
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s = g_malloc0(sizeof(rc4030State));
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@ -821,5 +896,19 @@ void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
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"rc4030.jazzio", 0x00001000);
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memory_region_add_subregion(sysmem, 0xf0000000, &s->iomem_jazzio);
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memory_region_init_rom_device(&s->dma_tt, NULL,
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&rc4030_dma_tt_ops, s, "dma-table",
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MAX_TL_ENTRIES * sizeof(dma_pagetable_entry),
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NULL);
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memory_region_init(&s->dma_tt_alias, NULL, "dma-table-alias", 0);
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memory_region_init(&s->dma_mr, NULL, "dma", INT32_MAX);
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for (i = 0; i < MAX_TL_ENTRIES; ++i) {
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memory_region_init_alias(&s->dma_mrs[i], NULL, "dma-alias",
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get_system_memory(), 0, DMA_PAGESIZE);
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memory_region_set_enabled(&s->dma_mrs[i], false);
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memory_region_add_subregion(&s->dma_mr, i * DMA_PAGESIZE,
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&s->dma_mrs[i]);
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}
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address_space_init(&s->dma_as, &s->dma_mr, "rc4030-dma");
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return s;
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}
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