Implement ARMv7 cp15 cache ID registers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6105 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -100,6 +100,9 @@ typedef struct CPUARMState {
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struct {
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struct {
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uint32_t c0_cpuid;
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uint32_t c0_cpuid;
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uint32_t c0_cachetype;
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uint32_t c0_cachetype;
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uint32_t c0_ccsid[16]; /* Cache size. */
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uint32_t c0_clid; /* Cache level. */
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uint32_t c0_cssel; /* Cache size selection. */
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uint32_t c0_c1[8]; /* Feature registers. */
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uint32_t c0_c1[8]; /* Feature registers. */
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uint32_t c0_c2[8]; /* Instruction set registers. */
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uint32_t c0_c2[8]; /* Instruction set registers. */
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uint32_t c1_sys; /* System control register. */
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uint32_t c1_sys; /* System control register. */
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@ -94,7 +94,11 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
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env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
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memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
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memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
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memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
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memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
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env->cp15.c0_cachetype = 0x1dd20d2;
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env->cp15.c0_cachetype = 0x82048004;
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env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
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env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
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env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
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env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
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break;
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break;
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case ARM_CPUID_CORTEXM3:
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case ARM_CPUID_CORTEXM3:
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set_feature(env, ARM_FEATURE_V6);
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set_feature(env, ARM_FEATURE_V6);
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@ -1321,15 +1325,16 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
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crm = insn & 0xf;
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crm = insn & 0xf;
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switch ((insn >> 16) & 0xf) {
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switch ((insn >> 16) & 0xf) {
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case 0:
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case 0:
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if (((insn >> 21) & 7) == 2) {
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/* ??? Select cache level. Ignore. */
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return;
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}
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/* ID codes. */
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/* ID codes. */
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if (arm_feature(env, ARM_FEATURE_XSCALE))
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if (arm_feature(env, ARM_FEATURE_XSCALE))
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break;
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break;
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if (arm_feature(env, ARM_FEATURE_OMAPCP))
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if (arm_feature(env, ARM_FEATURE_OMAPCP))
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break;
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break;
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if (arm_feature(env, ARM_FEATURE_V7)
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&& op1 == 2 && crm == 0 && op2 == 0) {
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env->cp15.c0_cssel = val & 0xf;
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break;
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}
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goto bad_reg;
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goto bad_reg;
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case 1: /* System configuration. */
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case 1: /* System configuration. */
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if (arm_feature(env, ARM_FEATURE_OMAPCP))
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if (arm_feature(env, ARM_FEATURE_OMAPCP))
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@ -1648,9 +1653,22 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
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goto bad_reg;
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goto bad_reg;
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if (crm != 0)
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if (crm != 0)
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goto bad_reg;
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goto bad_reg;
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if (arm_feature(env, ARM_FEATURE_XSCALE))
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if (!arm_feature(env, ARM_FEATURE_V7))
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goto bad_reg;
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return 0;
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return 0;
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switch (op2) {
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case 0:
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return env->cp15.c0_ccsid[env->cp15.c0_cssel];
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case 1:
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return env->cp15.c0_clid;
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case 7:
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return 0;
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}
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goto bad_reg;
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case 2:
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if (op2 != 0 || crm != 0)
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goto bad_reg;
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return env->cp15.c0_cssel;
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default:
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default:
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goto bad_reg;
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goto bad_reg;
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}
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}
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