target/mips: Style improvements in mips_fulong2e.c
Fixes mostly errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1566216496-17375-14-git-send-email-aleksandar.markovic@rt-rk.com>
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@ -83,14 +83,15 @@ static struct _loaderparams {
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const char *initrd_filename;
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} loaderparams;
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static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
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static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, int index,
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const char *string, ...)
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{
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va_list ap;
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int32_t table_addr;
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if (index >= ENVP_NB_ENTRIES)
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if (index >= ENVP_NB_ENTRIES) {
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return;
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}
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if (string == NULL) {
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prom_buf[index] = 0;
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@ -105,7 +106,7 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
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va_end(ap);
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}
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static int64_t load_kernel (CPUMIPSState *env)
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static int64_t load_kernel(CPUMIPSState *env)
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{
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int64_t kernel_entry, kernel_low, kernel_high, initrd_size;
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int index = 0;
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@ -130,16 +131,18 @@ static int64_t load_kernel (CPUMIPSState *env)
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initrd_size = 0;
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initrd_offset = 0;
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if (loaderparams.initrd_filename) {
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initrd_size = get_image_size (loaderparams.initrd_filename);
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initrd_size = get_image_size(loaderparams.initrd_filename);
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if (initrd_size > 0) {
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initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK;
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initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) &
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INITRD_PAGE_MASK;
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if (initrd_offset + initrd_size > ram_size) {
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error_report("memory too small for initial ram disk '%s'",
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loaderparams.initrd_filename);
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exit(1);
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}
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initrd_size = load_image_targphys(loaderparams.initrd_filename,
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initrd_offset, ram_size - initrd_offset);
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initrd_offset,
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ram_size - initrd_offset);
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}
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if (initrd_size == (target_ulong) -1) {
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error_report("could not load initial ram disk '%s'",
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@ -154,9 +157,10 @@ static int64_t load_kernel (CPUMIPSState *env)
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prom_set(prom_buf, index++, "%s", loaderparams.kernel_filename);
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if (initrd_size > 0) {
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prom_set(prom_buf, index++, "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
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cpu_mips_phys_to_kseg0(NULL, initrd_offset), initrd_size,
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loaderparams.kernel_cmdline);
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prom_set(prom_buf, index++,
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"rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
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cpu_mips_phys_to_kseg0(NULL, initrd_offset),
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initrd_size, loaderparams.kernel_cmdline);
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} else {
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prom_set(prom_buf, index++, "%s", loaderparams.kernel_cmdline);
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}
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@ -175,34 +179,48 @@ static int64_t load_kernel (CPUMIPSState *env)
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return kernel_entry;
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}
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static void write_bootloader (CPUMIPSState *env, uint8_t *base, int64_t kernel_addr)
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static void write_bootloader(CPUMIPSState *env, uint8_t *base,
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int64_t kernel_addr)
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{
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uint32_t *p;
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/* Small bootloader */
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p = (uint32_t *) base;
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p = (uint32_t *)base;
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stl_p(p++, 0x0bf00010); /* j 0x1fc00040 */
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stl_p(p++, 0x00000000); /* nop */
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/* j 0x1fc00040 */
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stl_p(p++, 0x0bf00010);
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/* nop */
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stl_p(p++, 0x00000000);
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/* Second part of the bootloader */
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p = (uint32_t *) (base + 0x040);
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p = (uint32_t *)(base + 0x040);
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stl_p(p++, 0x3c040000); /* lui a0, 0 */
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stl_p(p++, 0x34840002); /* ori a0, a0, 2 */
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stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
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stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a0, low(ENVP_ADDR) */
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stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
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stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
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stl_p(p++, 0x3c070000 | (loaderparams.ram_size >> 16)); /* lui a3, high(env->ram_size) */
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stl_p(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff)); /* ori a3, a3, low(env->ram_size) */
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stl_p(p++, 0x3c1f0000 | ((kernel_addr >> 16) & 0xffff)); /* lui ra, high(kernel_addr) */;
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stl_p(p++, 0x37ff0000 | (kernel_addr & 0xffff)); /* ori ra, ra, low(kernel_addr) */
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stl_p(p++, 0x03e00008); /* jr ra */
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stl_p(p++, 0x00000000); /* nop */
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/* lui a0, 0 */
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stl_p(p++, 0x3c040000);
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/* ori a0, a0, 2 */
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stl_p(p++, 0x34840002);
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/* lui a1, high(ENVP_ADDR) */
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stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff));
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/* ori a1, a0, low(ENVP_ADDR) */
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stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff));
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/* lui a2, high(ENVP_ADDR + 8) */
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stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff));
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/* ori a2, a2, low(ENVP_ADDR + 8) */
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stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff));
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/* lui a3, high(env->ram_size) */
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stl_p(p++, 0x3c070000 | (loaderparams.ram_size >> 16));
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/* ori a3, a3, low(env->ram_size) */
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stl_p(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff));
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/* lui ra, high(kernel_addr) */
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stl_p(p++, 0x3c1f0000 | ((kernel_addr >> 16) & 0xffff));
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/* ori ra, ra, low(kernel_addr) */
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stl_p(p++, 0x37ff0000 | (kernel_addr & 0xffff));
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/* jr ra */
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stl_p(p++, 0x03e00008);
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/* nop */
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stl_p(p++, 0x00000000);
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}
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static void main_cpu_reset(void *opaque)
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{
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MIPSCPU *cpu = opaque;
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@ -252,11 +270,11 @@ static void vt82c686b_southbridge_init(PCIBus *pci_bus, int slot, qemu_irq intc,
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}
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/* Network support */
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static void network_init (PCIBus *pci_bus)
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static void network_init(PCIBus *pci_bus)
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{
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int i;
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for(i = 0; i < nb_nics; i++) {
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for (i = 0; i < nb_nics; i++) {
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NICInfo *nd = &nd_table[i];
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const char *default_devaddr = NULL;
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@ -308,15 +326,17 @@ static void mips_fulong2e_init(MachineState *machine)
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memory_region_add_subregion(address_space_mem, 0, ram);
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memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios);
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/* We do not support flash operation, just loading pmon.bin as raw BIOS.
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* Please use -L to set the BIOS path and -bios to set bios name. */
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/*
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* We do not support flash operation, just loading pmon.bin as raw BIOS.
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* Please use -L to set the BIOS path and -bios to set bios name.
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*/
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if (kernel_filename) {
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loaderparams.ram_size = ram_size;
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loaderparams.kernel_filename = kernel_filename;
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loaderparams.kernel_cmdline = kernel_cmdline;
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loaderparams.initrd_filename = initrd_filename;
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kernel_entry = load_kernel (env);
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kernel_entry = load_kernel(env);
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write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry);
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} else {
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if (bios_name == NULL) {
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