s390x/mmu: Convert to non-recursive page table walk
A non-recursive implementation allows to make better use of the branch predictor, avoids function calls, and makes the implementation of new features only for a subset of region table levels easier. We can now directly compare our implementation to the KVM gaccess implementation in arch/s390/kvm/gaccess.c:guest_translate(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com>
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@ -114,107 +114,16 @@ static inline bool read_table_entry(CPUS390XState *env, hwaddr gaddr,
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return true;
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}
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/* Decode page table entry (normal 4KB page) */
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static int mmu_translate_pte(CPUS390XState *env, target_ulong vaddr,
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uint64_t asc, uint64_t pt_entry,
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target_ulong *raddr, int *flags, int rw, bool exc)
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{
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if (pt_entry & PAGE_ENTRY_I) {
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return PGM_PAGE_TRANS;
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}
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if (pt_entry & PAGE_ENTRY_0) {
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return PGM_TRANS_SPEC;
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}
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if (pt_entry & PAGE_ENTRY_P) {
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*flags &= ~PAGE_WRITE;
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}
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*raddr = pt_entry & TARGET_PAGE_MASK;
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return 0;
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}
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/* Decode segment table entry */
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static int mmu_translate_segment(CPUS390XState *env, target_ulong vaddr,
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uint64_t asc, uint64_t st_entry,
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target_ulong *raddr, int *flags, int rw,
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bool exc)
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{
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uint64_t origin, offs, pt_entry;
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if (st_entry & SEGMENT_ENTRY_P) {
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*flags &= ~PAGE_WRITE;
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}
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if ((st_entry & SEGMENT_ENTRY_FC) && (env->cregs[0] & CR0_EDAT)) {
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/* Decode EDAT1 segment frame absolute address (1MB page) */
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*raddr = (st_entry & SEGMENT_ENTRY_SFAA) |
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(vaddr & ~SEGMENT_ENTRY_SFAA);
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return 0;
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}
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/* Look up 4KB page entry */
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origin = st_entry & SEGMENT_ENTRY_ORIGIN;
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offs = VADDR_PAGE_TX(vaddr) * 8;
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if (!read_table_entry(env, origin + offs, &pt_entry)) {
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return PGM_ADDRESSING;
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}
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return mmu_translate_pte(env, vaddr, asc, pt_entry, raddr, flags, rw, exc);
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}
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/* Decode region table entries */
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static int mmu_translate_region(CPUS390XState *env, target_ulong vaddr,
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uint64_t asc, uint64_t entry, int level,
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target_ulong *raddr, int *flags, int rw,
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bool exc)
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{
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uint64_t origin, offs, new_entry;
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const int pchks[4] = {
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PGM_SEGMENT_TRANS, PGM_REG_THIRD_TRANS,
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PGM_REG_SEC_TRANS, PGM_REG_FIRST_TRANS
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};
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origin = entry & REGION_ENTRY_ORIGIN;
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offs = (vaddr >> (17 + 11 * level / 4)) & 0x3ff8;
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if (!read_table_entry(env, origin + offs, &new_entry)) {
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return PGM_ADDRESSING;
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}
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if (new_entry & REGION_ENTRY_I) {
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return pchks[level / 4];
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}
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if ((new_entry & REGION_ENTRY_TT) != level) {
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return PGM_TRANS_SPEC;
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}
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if (level == ASCE_TYPE_SEGMENT) {
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return mmu_translate_segment(env, vaddr, asc, new_entry, raddr, flags,
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rw, exc);
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}
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/* Check region table offset and length */
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offs = (vaddr >> (28 + 11 * (level - 4) / 4)) & 3;
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if (offs < ((new_entry & REGION_ENTRY_TF) >> 6)
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|| offs > (new_entry & REGION_ENTRY_TL)) {
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return pchks[level / 4 - 1];
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}
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if ((env->cregs[0] & CR0_EDAT) && (new_entry & REGION_ENTRY_P)) {
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*flags &= ~PAGE_WRITE;
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}
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/* yet another region */
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return mmu_translate_region(env, vaddr, asc, new_entry, level - 4,
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raddr, flags, rw, exc);
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}
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static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
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uint64_t asc, uint64_t asce, target_ulong *raddr,
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int *flags, int rw, bool exc)
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{
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const bool edat1 = (env->cregs[0] & CR0_EDAT) &&
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s390_has_feat(S390_FEAT_EDAT);
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const int asce_tl = asce & ASCE_TABLE_LENGTH;
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int level;
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const int asce_p = asce & ASCE_PRIVATE_SPACE;
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hwaddr gaddr = asce & ASCE_ORIGIN;
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uint64_t entry;
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if (asce & ASCE_REAL_SPACE) {
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/* direct mapping */
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@ -222,12 +131,12 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
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return 0;
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}
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level = asce & ASCE_TYPE_MASK;
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switch (level) {
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switch (asce & ASCE_TYPE_MASK) {
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case ASCE_TYPE_REGION1:
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if (VADDR_REGION1_TL(vaddr) > asce_tl) {
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return PGM_REG_FIRST_TRANS;
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}
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gaddr += VADDR_REGION1_TX(vaddr) * 8;
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break;
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case ASCE_TYPE_REGION2:
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if (VADDR_REGION1_TX(vaddr)) {
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@ -236,6 +145,7 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
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if (VADDR_REGION2_TL(vaddr) > asce_tl) {
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return PGM_REG_SEC_TRANS;
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}
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gaddr += VADDR_REGION2_TX(vaddr) * 8;
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break;
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case ASCE_TYPE_REGION3:
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if (VADDR_REGION1_TX(vaddr) || VADDR_REGION2_TX(vaddr)) {
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@ -244,6 +154,7 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
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if (VADDR_REGION3_TL(vaddr) > asce_tl) {
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return PGM_REG_THIRD_TRANS;
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}
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gaddr += VADDR_REGION3_TX(vaddr) * 8;
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break;
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case ASCE_TYPE_SEGMENT:
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if (VADDR_REGION1_TX(vaddr) || VADDR_REGION2_TX(vaddr) ||
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@ -253,11 +164,108 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
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if (VADDR_SEGMENT_TL(vaddr) > asce_tl) {
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return PGM_SEGMENT_TRANS;
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}
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gaddr += VADDR_SEGMENT_TX(vaddr) * 8;
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break;
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}
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return mmu_translate_region(env, vaddr, asc, asce, level, raddr, flags, rw,
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exc);
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switch (asce & ASCE_TYPE_MASK) {
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case ASCE_TYPE_REGION1:
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if (!read_table_entry(env, gaddr, &entry)) {
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return PGM_ADDRESSING;
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}
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if (entry & REGION_ENTRY_I) {
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return PGM_REG_FIRST_TRANS;
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}
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if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION1) {
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return PGM_TRANS_SPEC;
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}
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if (VADDR_REGION2_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||
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VADDR_REGION2_TL(vaddr) > (entry & REGION_ENTRY_TL)) {
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return PGM_REG_SEC_TRANS;
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}
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if (edat1 && (entry & REGION_ENTRY_P)) {
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*flags &= ~PAGE_WRITE;
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}
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gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_REGION2_TX(vaddr) * 8;
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/* fall through */
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case ASCE_TYPE_REGION2:
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if (!read_table_entry(env, gaddr, &entry)) {
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return PGM_ADDRESSING;
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}
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if (entry & REGION_ENTRY_I) {
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return PGM_REG_SEC_TRANS;
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}
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if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION2) {
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return PGM_TRANS_SPEC;
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}
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if (VADDR_REGION3_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||
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VADDR_REGION3_TL(vaddr) > (entry & REGION_ENTRY_TL)) {
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return PGM_REG_THIRD_TRANS;
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}
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if (edat1 && (entry & REGION_ENTRY_P)) {
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*flags &= ~PAGE_WRITE;
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}
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gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_REGION3_TX(vaddr) * 8;
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/* fall through */
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case ASCE_TYPE_REGION3:
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if (!read_table_entry(env, gaddr, &entry)) {
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return PGM_ADDRESSING;
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}
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if (entry & REGION_ENTRY_I) {
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return PGM_REG_THIRD_TRANS;
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}
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if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION3) {
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return PGM_TRANS_SPEC;
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}
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if (VADDR_SEGMENT_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||
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VADDR_SEGMENT_TL(vaddr) > (entry & REGION_ENTRY_TL)) {
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return PGM_SEGMENT_TRANS;
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}
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if (edat1 && (entry & REGION_ENTRY_P)) {
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*flags &= ~PAGE_WRITE;
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}
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gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_SEGMENT_TX(vaddr) * 8;
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/* fall through */
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case ASCE_TYPE_SEGMENT:
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if (!read_table_entry(env, gaddr, &entry)) {
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return PGM_ADDRESSING;
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}
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if (entry & SEGMENT_ENTRY_I) {
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return PGM_SEGMENT_TRANS;
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}
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if ((entry & SEGMENT_ENTRY_TT) != SEGMENT_ENTRY_TT_SEGMENT) {
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return PGM_TRANS_SPEC;
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}
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if ((entry & SEGMENT_ENTRY_CS) && asce_p) {
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return PGM_TRANS_SPEC;
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}
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if (entry & SEGMENT_ENTRY_P) {
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*flags &= ~PAGE_WRITE;
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}
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if (edat1 && (entry & SEGMENT_ENTRY_FC)) {
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*raddr = (entry & SEGMENT_ENTRY_SFAA) |
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(vaddr & ~SEGMENT_ENTRY_SFAA);
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return 0;
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}
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gaddr = (entry & SEGMENT_ENTRY_ORIGIN) + VADDR_PAGE_TX(vaddr) * 8;
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break;
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}
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if (!read_table_entry(env, gaddr, &entry)) {
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return PGM_ADDRESSING;
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}
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if (entry & PAGE_ENTRY_I) {
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return PGM_PAGE_TRANS;
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}
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if (entry & PAGE_ENTRY_0) {
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return PGM_TRANS_SPEC;
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}
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if (entry & PAGE_ENTRY_P) {
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*flags &= ~PAGE_WRITE;
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}
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*raddr = entry & TARGET_PAGE_MASK;
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return 0;
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}
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static void mmu_handle_skey(target_ulong addr, int rw, int *flags)
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