ppc: Implement bcdsr. instruction
bcdsr.: Decimal shift and round. This instruction works like bcds. however, when performing right shift, 1 will be added to the result if the last digit was >= 5. Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -395,6 +395,7 @@ DEF_HELPER_4(bcdcpsgn, i32, avr, avr, avr, i32)
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DEF_HELPER_3(bcdsetsgn, i32, avr, avr, i32)
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DEF_HELPER_4(bcds, i32, avr, avr, avr, i32)
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DEF_HELPER_4(bcdus, i32, avr, avr, avr, i32)
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DEF_HELPER_4(bcdsr, i32, avr, avr, avr, i32)
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DEF_HELPER_2(xsadddp, void, env, i32)
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DEF_HELPER_2(xsaddqp, void, env, i32)
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@ -3143,6 +3143,54 @@ uint32_t helper_bcdus(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
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return cr;
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}
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uint32_t helper_bcdsr(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
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{
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int cr;
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int unused = 0;
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int invalid = 0;
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bool ox_flag = false;
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int sgnb = bcd_get_sgn(b);
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ppc_avr_t ret = *b;
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ret.u64[LO_IDX] &= ~0xf;
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#if defined(HOST_WORDS_BIGENDIAN)
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int i = a->s8[7];
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ppc_avr_t bcd_one = { .u64 = { 0, 0x10 } };
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#else
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int i = a->s8[8];
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ppc_avr_t bcd_one = { .u64 = { 0x10, 0 } };
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#endif
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if (bcd_is_valid(b) == false) {
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return CRF_SO;
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}
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if (unlikely(i > 31)) {
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i = 31;
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} else if (unlikely(i < -31)) {
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i = -31;
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}
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if (i > 0) {
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ulshift(&ret.u64[LO_IDX], &ret.u64[HI_IDX], i * 4, &ox_flag);
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} else {
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urshift(&ret.u64[LO_IDX], &ret.u64[HI_IDX], -i * 4);
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if (bcd_get_digit(&ret, 0, &invalid) >= 5) {
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bcd_add_mag(&ret, &ret, &bcd_one, &invalid, &unused);
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}
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}
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bcd_put_digit(&ret, bcd_preferred_sgn(sgnb, ps), 0);
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cr = bcd_cmp_zero(&ret);
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if (ox_flag) {
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cr |= CRF_SO;
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}
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*r = ret;
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return cr;
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}
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void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
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{
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int i;
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@ -1018,6 +1018,7 @@ GEN_BCD2(bcdsetsgn)
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GEN_BCD(bcdcpsgn);
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GEN_BCD(bcds);
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GEN_BCD(bcdus);
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GEN_BCD(bcdsr);
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static void gen_xpnd04_1(DisasContext *ctx)
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{
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@ -132,6 +132,8 @@ GEN_HANDLER_E_2(vprtybd, 0x4, 0x1, 0x18, 9, 0, PPC_NONE, PPC2_ISA300),
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GEN_HANDLER_E_2(vprtybq, 0x4, 0x1, 0x18, 10, 0, PPC_NONE, PPC2_ISA300),
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GEN_VXFORM_DUAL(vsubcuw, xpnd04_1, 0, 22, PPC_ALTIVEC, PPC_NONE),
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GEN_VXFORM_300(bcdsr, 0, 23),
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GEN_VXFORM_300(bcdsr, 0, 31),
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GEN_VXFORM_DUAL(vaddubs, vmul10uq, 0, 8, PPC_ALTIVEC, PPC_NONE),
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GEN_VXFORM_DUAL(vadduhs, vmul10euq, 0, 9, PPC_ALTIVEC, PPC_NONE),
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GEN_VXFORM(vadduws, 0, 10),
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