target/sh4: split ctx->flags into ctx->tbflags and ctx->envflags
There is a confusion (and not only in the SH4 target) between tb->flags, env->flags and ctx->flags. To avoid it, split ctx->flags into ctx->tbflags and ctx->envflags. ctx->tbflags stays unchanged during the whole TB translation, while ctx->envflags evolves and is kept in sync with env->flags using TCG instructions. ctx->envflags now only contains the part that of env->flags that is contained in the TB state, i.e. the DELAY_SLOT* flags. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno
parent
ecc1f5adee
commit
a6215749dc
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@ -37,7 +37,8 @@ typedef struct DisasContext {
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struct TranslationBlock *tb;
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target_ulong pc;
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uint16_t opcode;
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uint32_t flags;
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uint32_t tbflags; /* should stay unmodified during the TB translation */
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uint32_t envflags; /* should stay in sync with env->flags using TCG ops */
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int bstate;
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int memidx;
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uint32_t delayed_pc;
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@ -49,7 +50,7 @@ typedef struct DisasContext {
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#if defined(CONFIG_USER_ONLY)
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#define IS_USER(ctx) 1
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#else
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#define IS_USER(ctx) (!(ctx->flags & (1u << SR_MD)))
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#define IS_USER(ctx) (!(ctx->tbflags & (1u << SR_MD)))
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#endif
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enum {
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@ -317,51 +318,50 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
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#define B11_8 ((ctx->opcode >> 8) & 0xf)
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#define B15_12 ((ctx->opcode >> 12) & 0xf)
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#define REG(x) ((x) < 8 && (ctx->flags & (1u << SR_MD))\
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&& (ctx->flags & (1u << SR_RB))\
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#define REG(x) ((x) < 8 && (ctx->tbflags & (1u << SR_MD))\
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&& (ctx->tbflags & (1u << SR_RB))\
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? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
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#define ALTREG(x) ((x) < 8 && (!(ctx->flags & (1u << SR_MD))\
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|| !(ctx->flags & (1u << SR_RB)))\
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#define ALTREG(x) ((x) < 8 && (!(ctx->tbflags & (1u << SR_MD))\
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|| !(ctx->tbflags & (1u << SR_RB)))\
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? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
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#define FREG(x) (ctx->flags & FPSCR_FR ? (x) ^ 0x10 : (x))
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#define FREG(x) (ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x))
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#define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
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#define XREG(x) (ctx->flags & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x))
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#define XREG(x) (ctx->tbflags & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x))
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#define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */
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#define CHECK_NOT_DELAY_SLOT \
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if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \
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{ \
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tcg_gen_movi_i32(cpu_pc, ctx->pc); \
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gen_helper_raise_slot_illegal_instruction(cpu_env); \
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ctx->bstate = BS_BRANCH; \
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return; \
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}
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if (ctx->envflags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
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tcg_gen_movi_i32(cpu_pc, ctx->pc); \
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gen_helper_raise_slot_illegal_instruction(cpu_env); \
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ctx->bstate = BS_BRANCH; \
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return; \
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}
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#define CHECK_PRIVILEGED \
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if (IS_USER(ctx)) { \
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tcg_gen_movi_i32(cpu_pc, ctx->pc); \
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if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
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gen_helper_raise_slot_illegal_instruction(cpu_env); \
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} else { \
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gen_helper_raise_illegal_instruction(cpu_env); \
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} \
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ctx->bstate = BS_BRANCH; \
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return; \
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}
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#define CHECK_PRIVILEGED \
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if (IS_USER(ctx)) { \
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tcg_gen_movi_i32(cpu_pc, ctx->pc); \
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if (ctx->envflags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
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gen_helper_raise_slot_illegal_instruction(cpu_env); \
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} else { \
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gen_helper_raise_illegal_instruction(cpu_env); \
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} \
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ctx->bstate = BS_BRANCH; \
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return; \
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}
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#define CHECK_FPU_ENABLED \
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if (ctx->flags & (1u << SR_FD)) { \
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tcg_gen_movi_i32(cpu_pc, ctx->pc); \
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if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
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gen_helper_raise_slot_fpu_disable(cpu_env); \
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} else { \
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gen_helper_raise_fpu_disable(cpu_env); \
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} \
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ctx->bstate = BS_BRANCH; \
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return; \
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}
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#define CHECK_FPU_ENABLED \
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if (ctx->tbflags & (1u << SR_FD)) { \
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tcg_gen_movi_i32(cpu_pc, ctx->pc); \
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if (ctx->envflags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
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gen_helper_raise_slot_fpu_disable(cpu_env); \
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} else { \
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gen_helper_raise_fpu_disable(cpu_env); \
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} \
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ctx->bstate = BS_BRANCH; \
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return; \
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}
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static void _decode_opc(DisasContext * ctx)
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{
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@ -409,7 +409,7 @@ static void _decode_opc(DisasContext * ctx)
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case 0x000b: /* rts */
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CHECK_NOT_DELAY_SLOT
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tcg_gen_mov_i32(cpu_delayed_pc, cpu_pr);
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ctx->flags |= DELAY_SLOT;
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ctx->envflags |= DELAY_SLOT;
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ctx->delayed_pc = (uint32_t) - 1;
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return;
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case 0x0028: /* clrmac */
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@ -431,7 +431,7 @@ static void _decode_opc(DisasContext * ctx)
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CHECK_NOT_DELAY_SLOT
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gen_write_sr(cpu_ssr);
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tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc);
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ctx->flags |= DELAY_SLOT;
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ctx->envflags |= DELAY_SLOT;
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ctx->delayed_pc = (uint32_t) - 1;
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return;
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case 0x0058: /* sets */
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@ -498,14 +498,14 @@ static void _decode_opc(DisasContext * ctx)
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CHECK_NOT_DELAY_SLOT
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ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2;
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tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc);
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ctx->flags |= DELAY_SLOT;
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ctx->envflags |= DELAY_SLOT;
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return;
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case 0xb000: /* bsr disp */
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CHECK_NOT_DELAY_SLOT
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tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
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ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2;
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tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc);
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ctx->flags |= DELAY_SLOT;
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ctx->envflags |= DELAY_SLOT;
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return;
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}
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@ -939,7 +939,7 @@ static void _decode_opc(DisasContext * ctx)
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return;
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case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
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CHECK_FPU_ENABLED
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if (ctx->flags & FPSCR_SZ) {
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if (ctx->tbflags & FPSCR_SZ) {
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TCGv_i64 fp = tcg_temp_new_i64();
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gen_load_fpr64(fp, XREG(B7_4));
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gen_store_fpr64(fp, XREG(B11_8));
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@ -950,7 +950,7 @@ static void _decode_opc(DisasContext * ctx)
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return;
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case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
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CHECK_FPU_ENABLED
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if (ctx->flags & FPSCR_SZ) {
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if (ctx->tbflags & FPSCR_SZ) {
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TCGv addr_hi = tcg_temp_new();
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int fr = XREG(B7_4);
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tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
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@ -966,7 +966,7 @@ static void _decode_opc(DisasContext * ctx)
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return;
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case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
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CHECK_FPU_ENABLED
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if (ctx->flags & FPSCR_SZ) {
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if (ctx->tbflags & FPSCR_SZ) {
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TCGv addr_hi = tcg_temp_new();
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int fr = XREG(B11_8);
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tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
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@ -980,7 +980,7 @@ static void _decode_opc(DisasContext * ctx)
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return;
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case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
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CHECK_FPU_ENABLED
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if (ctx->flags & FPSCR_SZ) {
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if (ctx->tbflags & FPSCR_SZ) {
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TCGv addr_hi = tcg_temp_new();
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int fr = XREG(B11_8);
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tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
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@ -998,7 +998,7 @@ static void _decode_opc(DisasContext * ctx)
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CHECK_FPU_ENABLED
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TCGv addr = tcg_temp_new_i32();
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tcg_gen_subi_i32(addr, REG(B11_8), 4);
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if (ctx->flags & FPSCR_SZ) {
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if (ctx->tbflags & FPSCR_SZ) {
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int fr = XREG(B7_4);
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tcg_gen_qemu_st_i32(cpu_fregs[fr+1], addr, ctx->memidx, MO_TEUL);
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tcg_gen_subi_i32(addr, addr, 4);
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@ -1015,7 +1015,7 @@ static void _decode_opc(DisasContext * ctx)
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{
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TCGv addr = tcg_temp_new_i32();
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tcg_gen_add_i32(addr, REG(B7_4), REG(0));
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if (ctx->flags & FPSCR_SZ) {
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if (ctx->tbflags & FPSCR_SZ) {
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int fr = XREG(B11_8);
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tcg_gen_qemu_ld_i32(cpu_fregs[fr], addr,
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ctx->memidx, MO_TEUL);
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@ -1034,7 +1034,7 @@ static void _decode_opc(DisasContext * ctx)
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{
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TCGv addr = tcg_temp_new();
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tcg_gen_add_i32(addr, REG(B11_8), REG(0));
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if (ctx->flags & FPSCR_SZ) {
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if (ctx->tbflags & FPSCR_SZ) {
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int fr = XREG(B7_4);
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tcg_gen_qemu_ld_i32(cpu_fregs[fr], addr,
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ctx->memidx, MO_TEUL);
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@ -1056,7 +1056,7 @@ static void _decode_opc(DisasContext * ctx)
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case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
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{
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CHECK_FPU_ENABLED
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if (ctx->flags & FPSCR_PR) {
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if (ctx->tbflags & FPSCR_PR) {
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TCGv_i64 fp0, fp1;
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if (ctx->opcode & 0x0110)
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@ -1125,7 +1125,7 @@ static void _decode_opc(DisasContext * ctx)
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case 0xf00e: /* fmac FR0,RM,Rn */
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{
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CHECK_FPU_ENABLED
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if (ctx->flags & FPSCR_PR) {
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if (ctx->tbflags & FPSCR_PR) {
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break; /* illegal instruction */
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} else {
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gen_helper_fmac_FT(cpu_fregs[FREG(B11_8)], cpu_env,
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@ -1162,7 +1162,7 @@ static void _decode_opc(DisasContext * ctx)
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case 0x8f00: /* bf/s label */
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CHECK_NOT_DELAY_SLOT
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gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 0);
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ctx->flags |= DELAY_SLOT_CONDITIONAL;
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ctx->envflags |= DELAY_SLOT_CONDITIONAL;
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return;
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case 0x8900: /* bt label */
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CHECK_NOT_DELAY_SLOT
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@ -1173,7 +1173,7 @@ static void _decode_opc(DisasContext * ctx)
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case 0x8d00: /* bt/s label */
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CHECK_NOT_DELAY_SLOT
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gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 1);
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ctx->flags |= DELAY_SLOT_CONDITIONAL;
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ctx->envflags |= DELAY_SLOT_CONDITIONAL;
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return;
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case 0x8800: /* cmp/eq #imm,R0 */
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tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, REG(0), B7_0s);
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@ -1354,14 +1354,14 @@ static void _decode_opc(DisasContext * ctx)
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case 0x0023: /* braf Rn */
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CHECK_NOT_DELAY_SLOT
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tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->pc + 4);
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ctx->flags |= DELAY_SLOT;
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ctx->envflags |= DELAY_SLOT;
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ctx->delayed_pc = (uint32_t) - 1;
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return;
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case 0x0003: /* bsrf Rn */
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CHECK_NOT_DELAY_SLOT
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tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
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tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr);
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ctx->flags |= DELAY_SLOT;
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ctx->envflags |= DELAY_SLOT;
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ctx->delayed_pc = (uint32_t) - 1;
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return;
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case 0x4015: /* cmp/pl Rn */
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@ -1377,14 +1377,14 @@ static void _decode_opc(DisasContext * ctx)
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case 0x402b: /* jmp @Rn */
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CHECK_NOT_DELAY_SLOT
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tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));
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ctx->flags |= DELAY_SLOT;
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ctx->envflags |= DELAY_SLOT;
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ctx->delayed_pc = (uint32_t) - 1;
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return;
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case 0x400b: /* jsr @Rn */
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CHECK_NOT_DELAY_SLOT
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tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
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tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));
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ctx->flags |= DELAY_SLOT;
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ctx->envflags |= DELAY_SLOT;
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ctx->delayed_pc = (uint32_t) - 1;
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return;
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case 0x400e: /* ldc Rm,SR */
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@ -1663,7 +1663,7 @@ static void _decode_opc(DisasContext * ctx)
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return;
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case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */
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CHECK_FPU_ENABLED
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if (ctx->flags & FPSCR_PR) {
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if (ctx->tbflags & FPSCR_PR) {
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TCGv_i64 fp;
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if (ctx->opcode & 0x0100)
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break; /* illegal instruction */
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@ -1678,7 +1678,7 @@ static void _decode_opc(DisasContext * ctx)
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return;
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case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
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CHECK_FPU_ENABLED
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if (ctx->flags & FPSCR_PR) {
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if (ctx->tbflags & FPSCR_PR) {
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TCGv_i64 fp;
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if (ctx->opcode & 0x0100)
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break; /* illegal instruction */
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@ -1699,7 +1699,7 @@ static void _decode_opc(DisasContext * ctx)
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return;
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case 0xf05d: /* fabs FRn/DRn */
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CHECK_FPU_ENABLED
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if (ctx->flags & FPSCR_PR) {
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if (ctx->tbflags & FPSCR_PR) {
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if (ctx->opcode & 0x0100)
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break; /* illegal instruction */
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TCGv_i64 fp = tcg_temp_new_i64();
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@ -1713,7 +1713,7 @@ static void _decode_opc(DisasContext * ctx)
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return;
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case 0xf06d: /* fsqrt FRn */
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CHECK_FPU_ENABLED
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if (ctx->flags & FPSCR_PR) {
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if (ctx->tbflags & FPSCR_PR) {
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if (ctx->opcode & 0x0100)
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break; /* illegal instruction */
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TCGv_i64 fp = tcg_temp_new_i64();
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@ -1731,13 +1731,13 @@ static void _decode_opc(DisasContext * ctx)
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break;
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case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
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CHECK_FPU_ENABLED
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if (!(ctx->flags & FPSCR_PR)) {
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if (!(ctx->tbflags & FPSCR_PR)) {
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tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0);
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}
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return;
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case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
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CHECK_FPU_ENABLED
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if (!(ctx->flags & FPSCR_PR)) {
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if (!(ctx->tbflags & FPSCR_PR)) {
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tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0x3f800000);
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}
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return;
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@ -1761,7 +1761,7 @@ static void _decode_opc(DisasContext * ctx)
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return;
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case 0xf0ed: /* fipr FVm,FVn */
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CHECK_FPU_ENABLED
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if ((ctx->flags & FPSCR_PR) == 0) {
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if ((ctx->tbflags & FPSCR_PR) == 0) {
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TCGv m, n;
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m = tcg_const_i32((ctx->opcode >> 8) & 3);
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n = tcg_const_i32((ctx->opcode >> 10) & 3);
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@ -1774,7 +1774,7 @@ static void _decode_opc(DisasContext * ctx)
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case 0xf0fd: /* ftrv XMTRX,FVn */
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CHECK_FPU_ENABLED
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if ((ctx->opcode & 0x0300) == 0x0100 &&
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(ctx->flags & FPSCR_PR) == 0) {
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(ctx->tbflags & FPSCR_PR) == 0) {
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TCGv n;
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n = tcg_const_i32((ctx->opcode >> 10) & 3);
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gen_helper_ftrv(cpu_env, n);
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@ -1789,7 +1789,7 @@ static void _decode_opc(DisasContext * ctx)
|
|||
fflush(stderr);
|
||||
#endif
|
||||
tcg_gen_movi_i32(cpu_pc, ctx->pc);
|
||||
if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
|
||||
if (ctx->envflags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
|
||||
gen_helper_raise_slot_illegal_instruction(cpu_env);
|
||||
} else {
|
||||
gen_helper_raise_illegal_instruction(cpu_env);
|
||||
|
|
@ -1799,20 +1799,20 @@ static void _decode_opc(DisasContext * ctx)
|
|||
|
||||
static void decode_opc(DisasContext * ctx)
|
||||
{
|
||||
uint32_t old_flags = ctx->flags;
|
||||
uint32_t old_flags = ctx->envflags;
|
||||
|
||||
_decode_opc(ctx);
|
||||
|
||||
if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
|
||||
if (ctx->flags & DELAY_SLOT_CLEARME) {
|
||||
if (ctx->envflags & DELAY_SLOT_CLEARME) {
|
||||
gen_store_flags(0);
|
||||
} else {
|
||||
/* go out of the delay slot */
|
||||
uint32_t new_flags = ctx->flags;
|
||||
uint32_t new_flags = ctx->envflags;
|
||||
new_flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
|
||||
gen_store_flags(new_flags);
|
||||
}
|
||||
ctx->flags = 0;
|
||||
ctx->envflags = 0;
|
||||
ctx->bstate = BS_BRANCH;
|
||||
if (old_flags & DELAY_SLOT_CONDITIONAL) {
|
||||
gen_delayed_conditional_jump(ctx);
|
||||
|
|
@ -1823,8 +1823,9 @@ static void decode_opc(DisasContext * ctx)
|
|||
}
|
||||
|
||||
/* go into a delay slot */
|
||||
if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL))
|
||||
gen_store_flags(ctx->flags);
|
||||
if (ctx->envflags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
|
||||
gen_store_flags(ctx->envflags);
|
||||
}
|
||||
}
|
||||
|
||||
void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
|
||||
|
|
@ -1838,16 +1839,18 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
|
|||
|
||||
pc_start = tb->pc;
|
||||
ctx.pc = pc_start;
|
||||
ctx.flags = (uint32_t)tb->flags;
|
||||
ctx.tbflags = (uint32_t)tb->flags;
|
||||
ctx.envflags = tb->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL |
|
||||
DELAY_SLOT_CLEARME);
|
||||
ctx.bstate = BS_NONE;
|
||||
ctx.memidx = (ctx.flags & (1u << SR_MD)) == 0 ? 1 : 0;
|
||||
ctx.memidx = (ctx.tbflags & (1u << SR_MD)) == 0 ? 1 : 0;
|
||||
/* We don't know if the delayed pc came from a dynamic or static branch,
|
||||
so assume it is a dynamic branch. */
|
||||
ctx.delayed_pc = -1; /* use delayed pc from env pointer */
|
||||
ctx.tb = tb;
|
||||
ctx.singlestep_enabled = cs->singlestep_enabled;
|
||||
ctx.features = env->features;
|
||||
ctx.has_movcal = (ctx.flags & TB_FLAG_PENDING_MOVCA);
|
||||
ctx.has_movcal = (ctx.tbflags & TB_FLAG_PENDING_MOVCA);
|
||||
|
||||
num_insns = 0;
|
||||
max_insns = tb->cflags & CF_COUNT_MASK;
|
||||
|
|
@ -1860,7 +1863,7 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
|
|||
|
||||
gen_tb_start(tb);
|
||||
while (ctx.bstate == BS_NONE && !tcg_op_buf_full()) {
|
||||
tcg_gen_insn_start(ctx.pc, ctx.flags);
|
||||
tcg_gen_insn_start(ctx.pc, ctx.envflags);
|
||||
num_insns++;
|
||||
|
||||
if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
|
||||
|
|
@ -1904,8 +1907,8 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
|
|||
/* gen_op_interrupt_restart(); */
|
||||
/* fall through */
|
||||
case BS_NONE:
|
||||
if (ctx.flags) {
|
||||
gen_store_flags(ctx.flags | DELAY_SLOT_CLEARME);
|
||||
if (ctx.envflags) {
|
||||
gen_store_flags(ctx.envflags | DELAY_SLOT_CLEARME);
|
||||
}
|
||||
gen_goto_tb(&ctx, 0, ctx.pc);
|
||||
break;
|
||||
|
|
|
|||
Loading…
Reference in a new issue