target/microblaze: Plug temp leaks for loads/stores
Simplify endian reversion of address also plugging TCG temp leaks for loads/stores. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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@ -962,17 +962,7 @@ static void dec_load(DisasContext *dc)
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switch (size) {
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switch (size) {
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case 1:
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case 1:
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{
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{
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/* 00 -> 11
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tcg_gen_xori_tl(addr, addr, 3);
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01 -> 10
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10 -> 10
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11 -> 00 */
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TCGv low = tcg_temp_new();
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tcg_gen_andi_tl(low, addr, 3);
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tcg_gen_sub_tl(low, tcg_const_tl(3), low);
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tcg_gen_andi_tl(addr, addr, ~3);
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tcg_gen_or_tl(addr, addr, low);
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tcg_temp_free(low);
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break;
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break;
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}
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}
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@ -1006,9 +996,16 @@ static void dec_load(DisasContext *dc)
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tcg_gen_qemu_ld_i32(v, addr, mem_index, mop);
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tcg_gen_qemu_ld_i32(v, addr, mem_index, mop);
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if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
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if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
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TCGv_i32 t0 = tcg_const_i32(0);
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TCGv_i32 treg = tcg_const_i32(dc->rd);
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TCGv_i32 tsize = tcg_const_i32(size - 1);
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tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc);
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tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc);
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gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd),
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gen_helper_memalign(cpu_env, addr, treg, t0, tsize);
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tcg_const_i32(0), tcg_const_i32(size - 1));
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tcg_temp_free_i32(t0);
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tcg_temp_free_i32(treg);
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tcg_temp_free_i32(tsize);
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}
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}
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if (ex) {
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if (ex) {
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@ -1095,17 +1092,7 @@ static void dec_store(DisasContext *dc)
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switch (size) {
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switch (size) {
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case 1:
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case 1:
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{
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{
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/* 00 -> 11
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tcg_gen_xori_tl(addr, addr, 3);
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01 -> 10
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10 -> 10
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11 -> 00 */
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TCGv low = tcg_temp_new();
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tcg_gen_andi_tl(low, addr, 3);
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tcg_gen_sub_tl(low, tcg_const_tl(3), low);
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tcg_gen_andi_tl(addr, addr, ~3);
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tcg_gen_or_tl(addr, addr, low);
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tcg_temp_free(low);
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break;
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break;
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}
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}
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@ -1124,6 +1111,10 @@ static void dec_store(DisasContext *dc)
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/* Verify alignment if needed. */
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/* Verify alignment if needed. */
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if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
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if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
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TCGv_i32 t1 = tcg_const_i32(1);
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TCGv_i32 treg = tcg_const_i32(dc->rd);
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TCGv_i32 tsize = tcg_const_i32(size - 1);
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tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc);
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tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc);
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/* FIXME: if the alignment is wrong, we should restore the value
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/* FIXME: if the alignment is wrong, we should restore the value
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* in memory. One possible way to achieve this is to probe
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* in memory. One possible way to achieve this is to probe
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@ -1131,8 +1122,11 @@ static void dec_store(DisasContext *dc)
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* the alignment checks in between the probe and the mem
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* the alignment checks in between the probe and the mem
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* access.
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* access.
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*/
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*/
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gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd),
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gen_helper_memalign(cpu_env, addr, treg, t1, tsize);
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tcg_const_i32(1), tcg_const_i32(size - 1));
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tcg_temp_free_i32(t1);
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tcg_temp_free_i32(treg);
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tcg_temp_free_i32(tsize);
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}
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}
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if (ex) {
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if (ex) {
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