allwinner-a10-pit: use level triggered interrupts
Convert the interrupt generation logic to the use of level triggered interrupts. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1395771730-16882-5-git-send-email-b.galvani@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -19,6 +19,15 @@
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#include "sysemu/sysemu.h"
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#include "sysemu/sysemu.h"
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#include "hw/timer/allwinner-a10-pit.h"
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#include "hw/timer/allwinner-a10-pit.h"
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static void a10_pit_update_irq(AwA10PITState *s)
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{
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int i;
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for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
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qemu_set_irq(s->irq[i], !!(s->irq_status & s->irq_enable & (1 << i)));
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}
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}
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static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size)
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static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size)
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{
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{
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AwA10PITState *s = AW_A10_PIT(opaque);
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AwA10PITState *s = AW_A10_PIT(opaque);
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@ -74,9 +83,11 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value,
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switch (offset) {
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switch (offset) {
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case AW_A10_PIT_TIMER_IRQ_EN:
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case AW_A10_PIT_TIMER_IRQ_EN:
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s->irq_enable = value;
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s->irq_enable = value;
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a10_pit_update_irq(s);
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break;
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break;
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case AW_A10_PIT_TIMER_IRQ_ST:
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case AW_A10_PIT_TIMER_IRQ_ST:
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s->irq_status &= ~value;
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s->irq_status &= ~value;
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a10_pit_update_irq(s);
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break;
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break;
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case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END:
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case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END:
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index = offset & 0xf0;
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index = offset & 0xf0;
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@ -178,6 +189,8 @@ static void a10_pit_reset(DeviceState *dev)
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s->irq_enable = 0;
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s->irq_enable = 0;
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s->irq_status = 0;
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s->irq_status = 0;
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a10_pit_update_irq(s);
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for (i = 0; i < 6; i++) {
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for (i = 0; i < 6; i++) {
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s->control[i] = AW_A10_PIT_DEFAULT_CLOCK;
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s->control[i] = AW_A10_PIT_DEFAULT_CLOCK;
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s->interval[i] = 0;
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s->interval[i] = 0;
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@ -203,7 +216,7 @@ static void a10_pit_timer_cb(void *opaque)
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ptimer_stop(s->timer[i]);
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ptimer_stop(s->timer[i]);
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s->control[i] &= ~AW_A10_PIT_TIMER_EN;
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s->control[i] &= ~AW_A10_PIT_TIMER_EN;
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}
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}
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qemu_irq_pulse(s->irq[i]);
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a10_pit_update_irq(s);
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}
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}
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}
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}
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