target/mips: Extract LSA/DLSA translation generators
Extract gen_lsa() from translate.c and explode it as gen_LSA() and gen_DLSA(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201215225757.764263-22-f4bug@amsat.org>
This commit is contained in:
parent
96e5b4c758
commit
a685f7d075
|
@ -17,6 +17,7 @@ mips_ss.add(when: 'CONFIG_TCG', if_true: files(
|
||||||
'op_helper.c',
|
'op_helper.c',
|
||||||
'tlb_helper.c',
|
'tlb_helper.c',
|
||||||
'translate.c',
|
'translate.c',
|
||||||
|
'translate_addr_const.c',
|
||||||
))
|
))
|
||||||
mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
|
mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
|
||||||
|
|
||||||
|
|
|
@ -6615,31 +6615,6 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
|
||||||
tcg_temp_free(t0);
|
tcg_temp_free(t0);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void gen_lsa(DisasContext *ctx, int opc, int rd, int rs, int rt,
|
|
||||||
int imm2)
|
|
||||||
{
|
|
||||||
TCGv t0;
|
|
||||||
TCGv t1;
|
|
||||||
if (rd == 0) {
|
|
||||||
/* Treat as NOP. */
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
t0 = tcg_temp_new();
|
|
||||||
t1 = tcg_temp_new();
|
|
||||||
gen_load_gpr(t0, rs);
|
|
||||||
gen_load_gpr(t1, rt);
|
|
||||||
tcg_gen_shli_tl(t0, t0, imm2 + 1);
|
|
||||||
tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
|
|
||||||
if (opc == OPC_LSA) {
|
|
||||||
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
|
|
||||||
}
|
|
||||||
|
|
||||||
tcg_temp_free(t1);
|
|
||||||
tcg_temp_free(t0);
|
|
||||||
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs,
|
static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs,
|
||||||
int rt, int bits)
|
int rt, int bits)
|
||||||
{
|
{
|
||||||
|
@ -16495,8 +16470,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
|
||||||
return;
|
return;
|
||||||
case LSA:
|
case LSA:
|
||||||
check_insn(ctx, ISA_MIPS_R6);
|
check_insn(ctx, ISA_MIPS_R6);
|
||||||
gen_lsa(ctx, OPC_LSA, rd, rs, rt,
|
gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2));
|
||||||
extract32(ctx->opcode, 9, 2));
|
|
||||||
break;
|
break;
|
||||||
case ALIGN:
|
case ALIGN:
|
||||||
check_insn(ctx, ISA_MIPS_R6);
|
check_insn(ctx, ISA_MIPS_R6);
|
||||||
|
@ -21459,8 +21433,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
|
||||||
* amount, meaning that the supported shift values are in
|
* amount, meaning that the supported shift values are in
|
||||||
* the range 0 to 3 (instead of 1 to 4 in MIPSR6).
|
* the range 0 to 3 (instead of 1 to 4 in MIPSR6).
|
||||||
*/
|
*/
|
||||||
gen_lsa(ctx, OPC_LSA, rd, rs, rt,
|
gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2) - 1);
|
||||||
extract32(ctx->opcode, 9, 2) - 1);
|
|
||||||
break;
|
break;
|
||||||
case NM_EXTW:
|
case NM_EXTW:
|
||||||
gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5));
|
gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5));
|
||||||
|
@ -24346,7 +24319,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
|
||||||
op1 = MASK_SPECIAL(ctx->opcode);
|
op1 = MASK_SPECIAL(ctx->opcode);
|
||||||
switch (op1) {
|
switch (op1) {
|
||||||
case OPC_LSA:
|
case OPC_LSA:
|
||||||
gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2));
|
gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 6, 2));
|
||||||
break;
|
break;
|
||||||
case OPC_MULT:
|
case OPC_MULT:
|
||||||
case OPC_MULTU:
|
case OPC_MULTU:
|
||||||
|
@ -24399,8 +24372,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
|
||||||
break;
|
break;
|
||||||
#if defined(TARGET_MIPS64)
|
#if defined(TARGET_MIPS64)
|
||||||
case OPC_DLSA:
|
case OPC_DLSA:
|
||||||
check_mips_64(ctx);
|
gen_dlsa(ctx, rd, rt, rs, extract32(ctx->opcode, 6, 2));
|
||||||
gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2));
|
|
||||||
break;
|
break;
|
||||||
case R6_OPC_DCLO:
|
case R6_OPC_DCLO:
|
||||||
case R6_OPC_DCLZ:
|
case R6_OPC_DCLZ:
|
||||||
|
|
|
@ -137,7 +137,12 @@ void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg);
|
||||||
void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
|
void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
|
||||||
int get_fp_bit(int cc);
|
int get_fp_bit(int cc);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Address Computation and Large Constant Instructions
|
||||||
|
*/
|
||||||
void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1);
|
void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1);
|
||||||
|
bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
|
||||||
|
bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
|
||||||
|
|
||||||
extern TCGv cpu_gpr[32], cpu_PC;
|
extern TCGv cpu_gpr[32], cpu_PC;
|
||||||
extern TCGv_i32 fpu_fcr0, fpu_fcr31;
|
extern TCGv_i32 fpu_fcr0, fpu_fcr31;
|
||||||
|
|
61
target/mips/translate_addr_const.c
Normal file
61
target/mips/translate_addr_const.c
Normal file
|
@ -0,0 +1,61 @@
|
||||||
|
/*
|
||||||
|
* Address Computation and Large Constant Instructions
|
||||||
|
*
|
||||||
|
* Copyright (c) 2004-2005 Jocelyn Mayer
|
||||||
|
* Copyright (c) 2006 Marius Groeger (FPU operations)
|
||||||
|
* Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
|
||||||
|
* Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
|
||||||
|
* Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
|
||||||
|
* Copyright (c) 2020 Philippe Mathieu-Daudé
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: LGPL-2.1-or-later
|
||||||
|
*/
|
||||||
|
#include "qemu/osdep.h"
|
||||||
|
#include "tcg/tcg-op.h"
|
||||||
|
#include "translate.h"
|
||||||
|
|
||||||
|
bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
|
||||||
|
{
|
||||||
|
TCGv t0;
|
||||||
|
TCGv t1;
|
||||||
|
|
||||||
|
if (rd == 0) {
|
||||||
|
/* Treat as NOP. */
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
t0 = tcg_temp_new();
|
||||||
|
t1 = tcg_temp_new();
|
||||||
|
gen_load_gpr(t0, rs);
|
||||||
|
gen_load_gpr(t1, rt);
|
||||||
|
tcg_gen_shli_tl(t0, t0, sa + 1);
|
||||||
|
tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
|
||||||
|
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
|
||||||
|
|
||||||
|
tcg_temp_free(t1);
|
||||||
|
tcg_temp_free(t0);
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
|
||||||
|
{
|
||||||
|
TCGv t0;
|
||||||
|
TCGv t1;
|
||||||
|
|
||||||
|
check_mips_64(ctx);
|
||||||
|
|
||||||
|
if (rd == 0) {
|
||||||
|
/* Treat as NOP. */
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
t0 = tcg_temp_new();
|
||||||
|
t1 = tcg_temp_new();
|
||||||
|
gen_load_gpr(t0, rs);
|
||||||
|
gen_load_gpr(t1, rt);
|
||||||
|
tcg_gen_shli_tl(t0, t0, sa + 1);
|
||||||
|
tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
|
||||||
|
tcg_temp_free(t1);
|
||||||
|
tcg_temp_free(t0);
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
Loading…
Reference in a new issue