ppc: Add POWER8 IAMR register
With appropriate AMR-like masks. Not actually used by the translation logic at that point Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: changed spr_register_hv(SPR_IAMR) to spr_register_kvm_hv(SPR_IAMR) changed gen_spr_amr() prototype ] Signed-off-by: Cédric Le Goater <clg@fr.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -1360,6 +1360,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
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#define SPR_BOOKE_CSRR0 (0x03A)
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#define SPR_BOOKE_CSRR1 (0x03B)
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#define SPR_BOOKE_DEAR (0x03D)
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#define SPR_IAMR (0x03D)
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#define SPR_BOOKE_ESR (0x03E)
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#define SPR_BOOKE_IVPR (0x03F)
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#define SPR_MPC_EIE (0x050)
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@ -1126,9 +1126,39 @@ static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
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tcg_temp_free(t1);
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tcg_temp_free(t2);
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}
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static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
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{
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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TCGv t2 = tcg_temp_new();
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/* Note, the HV=1 case is handled earlier by simply using
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* spr_write_generic for HV mode in the SPR table
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*/
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/* Build insertion mask into t1 based on context */
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gen_load_spr(t1, SPR_AMOR);
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/* Mask new bits into t2 */
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tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
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/* Load AMR and clear new bits in t0 */
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gen_load_spr(t0, SPR_IAMR);
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tcg_gen_andc_tl(t0, t0, t1);
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/* Or'in new bits and write it out */
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tcg_gen_or_tl(t0, t0, t2);
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gen_store_spr(SPR_IAMR, t0);
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spr_store_dump_spr(SPR_IAMR);
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tcg_temp_free(t0);
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tcg_temp_free(t1);
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tcg_temp_free(t2);
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}
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#endif /* CONFIG_USER_ONLY */
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static void gen_spr_amr (CPUPPCState *env)
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static void gen_spr_amr(CPUPPCState *env, bool has_iamr)
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{
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#ifndef CONFIG_USER_ONLY
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/* Virtual Page Class Key protection */
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@ -1154,6 +1184,13 @@ static void gen_spr_amr (CPUPPCState *env)
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0);
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if (has_iamr) {
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spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_iamr,
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&spr_read_generic, &spr_write_generic,
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KVM_REG_PPC_IAMR, 0);
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}
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#endif /* !CONFIG_USER_ONLY */
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}
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#endif /* TARGET_PPC64 */
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@ -8000,7 +8037,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
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case BOOK3S_CPU_POWER7:
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case BOOK3S_CPU_POWER8:
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gen_spr_book3s_ids(env);
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gen_spr_amr(env);
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gen_spr_amr(env, version >= BOOK3S_CPU_POWER8);
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gen_spr_book3s_purr(env);
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env->ci_large_pages = true;
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break;
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