target/arm: Optimize MVE VSHLL and VMOVL
Optimize the MVE VSHLL insns by using TCG vector ops when possible. This includes the VMOVL insn, which we handle in mve.decode as "VSHLL with zero shift count". Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210913095440.13462-11-peter.maydell@linaro.org
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@ -1742,7 +1742,58 @@ DO_2SHIFT_SCALAR(VQRSHL_U_scalar, vqrshli_u)
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gen_helper_mve_##FN##b, \
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gen_helper_mve_##FN##h, \
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}; \
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return do_2shift(s, a, fns[a->size], false); \
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return do_2shift_vec(s, a, fns[a->size], false, do_gvec_##FN); \
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}
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/*
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* For the VSHLL vector helpers, the vece is the size of the input
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* (ie MO_8 or MO_16); the helpers want to work in the output size.
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* The shift count can be 0..<input size>, inclusive. (0 is VMOVL.)
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*/
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static void do_gvec_vshllbs(unsigned vece, uint32_t dofs, uint32_t aofs,
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int64_t shift, uint32_t oprsz, uint32_t maxsz)
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{
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unsigned ovece = vece + 1;
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unsigned ibits = vece == MO_8 ? 8 : 16;
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tcg_gen_gvec_shli(ovece, dofs, aofs, ibits, oprsz, maxsz);
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tcg_gen_gvec_sari(ovece, dofs, dofs, ibits - shift, oprsz, maxsz);
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}
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static void do_gvec_vshllbu(unsigned vece, uint32_t dofs, uint32_t aofs,
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int64_t shift, uint32_t oprsz, uint32_t maxsz)
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{
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unsigned ovece = vece + 1;
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tcg_gen_gvec_andi(ovece, dofs, aofs,
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ovece == MO_16 ? 0xff : 0xffff, oprsz, maxsz);
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tcg_gen_gvec_shli(ovece, dofs, dofs, shift, oprsz, maxsz);
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}
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static void do_gvec_vshllts(unsigned vece, uint32_t dofs, uint32_t aofs,
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int64_t shift, uint32_t oprsz, uint32_t maxsz)
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{
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unsigned ovece = vece + 1;
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unsigned ibits = vece == MO_8 ? 8 : 16;
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if (shift == 0) {
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tcg_gen_gvec_sari(ovece, dofs, aofs, ibits, oprsz, maxsz);
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} else {
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tcg_gen_gvec_andi(ovece, dofs, aofs,
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ovece == MO_16 ? 0xff00 : 0xffff0000, oprsz, maxsz);
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tcg_gen_gvec_sari(ovece, dofs, dofs, ibits - shift, oprsz, maxsz);
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}
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}
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static void do_gvec_vshlltu(unsigned vece, uint32_t dofs, uint32_t aofs,
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int64_t shift, uint32_t oprsz, uint32_t maxsz)
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{
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unsigned ovece = vece + 1;
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unsigned ibits = vece == MO_8 ? 8 : 16;
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if (shift == 0) {
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tcg_gen_gvec_shri(ovece, dofs, aofs, ibits, oprsz, maxsz);
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} else {
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tcg_gen_gvec_andi(ovece, dofs, aofs,
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ovece == MO_16 ? 0xff00 : 0xffff0000, oprsz, maxsz);
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tcg_gen_gvec_shri(ovece, dofs, dofs, ibits - shift, oprsz, maxsz);
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}
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}
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DO_VSHLL(VSHLL_BS, vshllbs)
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