target-ppc: Add Flag for ISA2.06 Divide Extended Instructions
This patch adds a flag for the Divide Extended instructions that were introduced in Power ISA V2.06B. The flag is added to the Power7 and Power8 models. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
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@ -1879,9 +1879,12 @@ enum {
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PPC2_VSX207 = 0x0000000000000040ULL,
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PPC2_VSX207 = 0x0000000000000040ULL,
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/* ISA 2.06B bpermd */
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/* ISA 2.06B bpermd */
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PPC2_PERM_ISA206 = 0x0000000000000080ULL,
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PPC2_PERM_ISA206 = 0x0000000000000080ULL,
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/* ISA 2.06B divide extended variants */
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PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
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#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
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#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
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PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206)
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PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
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PPC2_DIVE_ISA206)
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};
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};
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/*****************************************************************************/
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/*****************************************************************************/
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@ -7069,7 +7069,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
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PPC_SEGMENT_64B | PPC_SLBI |
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PPC_SEGMENT_64B | PPC_SLBI |
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PPC_POPCNTB | PPC_POPCNTWD;
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PPC_POPCNTB | PPC_POPCNTWD;
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pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
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pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
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PPC2_PERM_ISA206;
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PPC2_PERM_ISA206 | PPC2_DIVE_ISA206;
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pcc->msr_mask = 0x800000000284FF37ULL;
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pcc->msr_mask = 0x800000000284FF37ULL;
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pcc->mmu_model = POWERPC_MMU_2_06;
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pcc->mmu_model = POWERPC_MMU_2_06;
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#if defined(CONFIG_SOFTMMU)
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#if defined(CONFIG_SOFTMMU)
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@ -7108,7 +7108,7 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
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PPC_SEGMENT_64B | PPC_SLBI |
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PPC_SEGMENT_64B | PPC_SLBI |
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PPC_POPCNTB | PPC_POPCNTWD;
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PPC_POPCNTB | PPC_POPCNTWD;
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pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
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pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
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PPC2_PERM_ISA206;
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PPC2_PERM_ISA206 | PPC2_DIVE_ISA206;
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pcc->msr_mask = 0x800000000204FF37ULL;
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pcc->msr_mask = 0x800000000204FF37ULL;
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pcc->mmu_model = POWERPC_MMU_2_06;
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pcc->mmu_model = POWERPC_MMU_2_06;
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#if defined(CONFIG_SOFTMMU)
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#if defined(CONFIG_SOFTMMU)
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@ -7147,7 +7147,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
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PPC_SEGMENT_64B | PPC_SLBI |
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PPC_SEGMENT_64B | PPC_SLBI |
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PPC_POPCNTB | PPC_POPCNTWD;
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PPC_POPCNTB | PPC_POPCNTWD;
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pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
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pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
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PPC2_PERM_ISA206;
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PPC2_PERM_ISA206 | PPC2_DIVE_ISA206;
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pcc->msr_mask = 0x800000000284FF36ULL;
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pcc->msr_mask = 0x800000000284FF36ULL;
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pcc->mmu_model = POWERPC_MMU_2_06;
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pcc->mmu_model = POWERPC_MMU_2_06;
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#if defined(CONFIG_SOFTMMU)
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#if defined(CONFIG_SOFTMMU)
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