sdhci: use a numeric value for the default CAPAB register
using many #defines is not portable when scaling to different HCI. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-9-f4bug@amsat.org>
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@ -38,67 +38,25 @@
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#define TYPE_SDHCI_BUS "sdhci-bus"
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#define TYPE_SDHCI_BUS "sdhci-bus"
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#define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS)
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#define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS)
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#define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
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/* Default SD/MMC host controller features information, which will be
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/* Default SD/MMC host controller features information, which will be
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* presented in CAPABILITIES register of generic SD host controller at reset.
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* presented in CAPABILITIES register of generic SD host controller at reset.
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* If not stated otherwise:
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*
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* 0 - not supported, 1 - supported, other - prohibited.
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* support:
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* - 3.3v and 1.8v voltages
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* - SDMA/ADMA1/ADMA2
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* - high-speed
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* max host controller R/W buffers size: 512B
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* max clock frequency for SDclock: 52 MHz
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* timeout clock frequency: 52 MHz
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*
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* does not support:
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* - 3.0v voltage
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* - 64-bit system bus
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* - suspend/resume
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*/
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*/
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#define SDHC_CAPAB_64BITBUS 0ul /* 64-bit System Bus Support */
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#define SDHC_CAPAB_REG_DEFAULT 0x057834b4
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#define SDHC_CAPAB_18V 1ul /* Voltage support 1.8v */
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#define SDHC_CAPAB_30V 0ul /* Voltage support 3.0v */
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#define SDHC_CAPAB_33V 1ul /* Voltage support 3.3v */
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#define SDHC_CAPAB_SUSPRESUME 0ul /* Suspend/resume support */
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#define SDHC_CAPAB_SDMA 1ul /* SDMA support */
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#define SDHC_CAPAB_HIGHSPEED 1ul /* High speed support */
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#define SDHC_CAPAB_ADMA1 1ul /* ADMA1 support */
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#define SDHC_CAPAB_ADMA2 1ul /* ADMA2 support */
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/* Maximum host controller R/W buffers size
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* Possible values: 512, 1024, 2048 bytes */
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#define SDHC_CAPAB_MAXBLOCKLENGTH 512ul
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/* Maximum clock frequency for SDclock in MHz
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* value in range 10-63 MHz, 0 - not defined */
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#define SDHC_CAPAB_BASECLKFREQ 52ul
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#define SDHC_CAPAB_TOUNIT 1ul /* Timeout clock unit 0 - kHz, 1 - MHz */
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/* Timeout clock frequency 1-63, 0 - not defined */
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#define SDHC_CAPAB_TOCLKFREQ 52ul
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/* Now check all parameters and calculate CAPABILITIES REGISTER value */
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#if SDHC_CAPAB_64BITBUS > 1 || SDHC_CAPAB_18V > 1 || SDHC_CAPAB_30V > 1 || \
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SDHC_CAPAB_33V > 1 || SDHC_CAPAB_SUSPRESUME > 1 || SDHC_CAPAB_SDMA > 1 || \
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SDHC_CAPAB_HIGHSPEED > 1 || SDHC_CAPAB_ADMA2 > 1 || SDHC_CAPAB_ADMA1 > 1 ||\
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SDHC_CAPAB_TOUNIT > 1
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#error Capabilities features can have value 0 or 1 only!
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#endif
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#if SDHC_CAPAB_MAXBLOCKLENGTH == 512
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#define MAX_BLOCK_LENGTH 0ul
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#elif SDHC_CAPAB_MAXBLOCKLENGTH == 1024
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#define MAX_BLOCK_LENGTH 1ul
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#elif SDHC_CAPAB_MAXBLOCKLENGTH == 2048
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#define MAX_BLOCK_LENGTH 2ul
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#else
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#error Max host controller block size can have value 512, 1024 or 2048 only!
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#endif
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#if (SDHC_CAPAB_BASECLKFREQ > 0 && SDHC_CAPAB_BASECLKFREQ < 10) || \
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SDHC_CAPAB_BASECLKFREQ > 63
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#error SDclock frequency can have value in range 0, 10-63 only!
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#endif
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#if SDHC_CAPAB_TOCLKFREQ > 63
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#error Timeout clock frequency can have value in range 0-63 only!
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#endif
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#define SDHC_CAPAB_REG_DEFAULT \
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((SDHC_CAPAB_64BITBUS << 28) | (SDHC_CAPAB_18V << 26) | \
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(SDHC_CAPAB_30V << 25) | (SDHC_CAPAB_33V << 24) | \
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(SDHC_CAPAB_SUSPRESUME << 23) | (SDHC_CAPAB_SDMA << 22) | \
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(SDHC_CAPAB_HIGHSPEED << 21) | (SDHC_CAPAB_ADMA1 << 20) | \
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(SDHC_CAPAB_ADMA2 << 19) | (MAX_BLOCK_LENGTH << 16) | \
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(SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \
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(SDHC_CAPAB_TOCLKFREQ))
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#define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
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static uint8_t sdhci_slotint(SDHCIState *s)
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static uint8_t sdhci_slotint(SDHCIState *s)
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{
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{
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