target-ppc: move out stqcx impementation
Being a 16byte operation, qemu_ld/st still does not support this. Move this out so other store operation can use qemu_ld/st in the following patch. Also, convert it to two MO_Q operations for stqcx. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -3105,22 +3105,6 @@ static void gen_conditional_store(DisasContext *ctx, TCGv EA,
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gen_qemu_st32(ctx, cpu_gpr[reg], EA);
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} else if (size == 2) {
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gen_qemu_st16(ctx, cpu_gpr[reg], EA);
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#if defined(TARGET_PPC64)
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} else if (size == 16) {
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TCGv gpr1, gpr2 , EA8;
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if (unlikely(ctx->le_mode)) {
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gpr1 = cpu_gpr[reg+1];
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gpr2 = cpu_gpr[reg];
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} else {
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gpr1 = cpu_gpr[reg];
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gpr2 = cpu_gpr[reg+1];
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}
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gen_qemu_st64_i64(ctx, gpr1, EA);
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EA8 = tcg_temp_local_new();
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gen_addr_add(ctx, EA8, EA, 8);
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gen_qemu_st64_i64(ctx, gpr2, EA8);
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tcg_temp_free(EA8);
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#endif
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} else {
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gen_qemu_st8(ctx, cpu_gpr[reg], EA);
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}
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@ -3133,11 +3117,6 @@ static void gen_conditional_store(DisasContext *ctx, TCGv EA,
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static void gen_##name(DisasContext *ctx) \
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{ \
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TCGv t0; \
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if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
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gen_inval_exception(ctx, \
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POWERPC_EXCP_INVAL_INVAL); \
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return; \
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} \
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gen_set_access_type(ctx, ACCESS_RES); \
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t0 = tcg_temp_local_new(); \
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gen_addr_reg_index(ctx, t0); \
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@ -3190,9 +3169,55 @@ static void gen_lqarx(DisasContext *ctx)
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tcg_temp_free(EA);
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}
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/* stqcx. */
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static void gen_stqcx_(DisasContext *ctx)
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{
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TCGv EA;
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int reg = rS(ctx->opcode);
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int len = 16;
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#if !defined(CONFIG_USER_ONLY)
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TCGLabel *l1;
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TCGv gpr1, gpr2;
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#endif
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if (unlikely((rD(ctx->opcode) & 1))) {
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gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
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return;
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}
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gen_set_access_type(ctx, ACCESS_RES);
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EA = tcg_temp_local_new();
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gen_addr_reg_index(ctx, EA);
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if (len > 1) {
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gen_check_align(ctx, EA, (len) - 1);
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}
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#if defined(CONFIG_USER_ONLY)
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gen_conditional_store(ctx, EA, reg, 16);
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#else
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tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
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l1 = gen_new_label();
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tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
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tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
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if (unlikely(ctx->le_mode)) {
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gpr1 = cpu_gpr[reg + 1];
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gpr2 = cpu_gpr[reg];
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} else {
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gpr1 = cpu_gpr[reg];
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gpr2 = cpu_gpr[reg + 1];
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}
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tcg_gen_qemu_st_tl(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
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gen_addr_add(ctx, EA, EA, 8);
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tcg_gen_qemu_st_tl(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
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gen_set_label(l1);
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tcg_gen_movi_tl(cpu_reserve, -1);
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#endif
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tcg_temp_free(EA);
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}
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/* stdcx. */
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STCX(stdcx_, 8);
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STCX(stqcx_, 16);
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#endif /* defined(TARGET_PPC64) */
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/* sync */
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