haraldwolff/qemu-patch-raspberry4
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Merge branch 'for-anthony' of git://github.com/bonzini/qemu

Browse source 
* 'for-anthony' of git://github.com/bonzini/qemu:
  remove qemu_get_clock
  add a generic scaling mechanism for timers
  change all other clock references to use nanosecond resolution accessors
  change all rt_clock references to use millisecond resolution accessors
  add more helper functions with explicit milli/nanosecond resolution
This commit is contained in:
Aurelien Jarno 2011-03-21 21:28:38 +01:00
parent 3246572762 6d5ad9bf93
commit aa315f95b7
79 changed files with 363 additions and 350 deletions
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4
audio/audio.c
View file

@ -1114,7 +1114,7 @@ static int audio_is_timer_needed (void)
static void audio_reset_timer (AudioState *s) static void audio_reset_timer (AudioState *s)
{ {
if (audio_is_timer_needed ()) { if (audio_is_timer_needed ()) {
qemu_mod_timer (s->ts, qemu_get_clock (vm_clock) + 1); qemu_mod_timer (s->ts, qemu_get_clock_ns (vm_clock) + 1);
} }
else { else {
qemu_del_timer (s->ts); qemu_del_timer (s->ts);
@ -1820,7 +1820,7 @@ static void audio_init (void)
QLIST_INIT (&s->cap_head); QLIST_INIT (&s->cap_head);
atexit (audio_atexit); atexit (audio_atexit);
s->ts = qemu_new_timer (vm_clock, audio_timer, s); s->ts = qemu_new_timer_ns (vm_clock, audio_timer, s);
if (!s->ts) { if (!s->ts) {
hw_error("Could not create audio timer\n"); hw_error("Could not create audio timer\n");
} }

4
audio/noaudio.c
View file

@ -46,7 +46,7 @@ static int no_run_out (HWVoiceOut *hw, int live)
int64_t ticks; int64_t ticks;
int64_t bytes; int64_t bytes;
now = qemu_get_clock (vm_clock); now = qemu_get_clock_ns (vm_clock);
ticks = now - no->old_ticks; ticks = now - no->old_ticks;
bytes = muldiv64 (ticks, hw->info.bytes_per_second, get_ticks_per_sec ()); bytes = muldiv64 (ticks, hw->info.bytes_per_second, get_ticks_per_sec ());
bytes = audio_MIN (bytes, INT_MAX); bytes = audio_MIN (bytes, INT_MAX);
@ -102,7 +102,7 @@ static int no_run_in (HWVoiceIn *hw)
int samples = 0; int samples = 0;
if (dead) { if (dead) {
int64_t now = qemu_get_clock (vm_clock); int64_t now = qemu_get_clock_ns (vm_clock);
int64_t ticks = now - no->old_ticks; int64_t ticks = now - no->old_ticks;
int64_t bytes = int64_t bytes =
muldiv64 (ticks, hw->info.bytes_per_second, get_ticks_per_sec ()); muldiv64 (ticks, hw->info.bytes_per_second, get_ticks_per_sec ());

4
audio/spiceaudio.c
View file

@ -81,7 +81,7 @@ static void spice_audio_fini (void *opaque)
static void rate_start (SpiceRateCtl *rate) static void rate_start (SpiceRateCtl *rate)
{ {
memset (rate, 0, sizeof (*rate)); memset (rate, 0, sizeof (*rate));
rate->start_ticks = qemu_get_clock (vm_clock); rate->start_ticks = qemu_get_clock_ns (vm_clock);
} }
static int rate_get_samples (struct audio_pcm_info *info, SpiceRateCtl *rate) static int rate_get_samples (struct audio_pcm_info *info, SpiceRateCtl *rate)
@ -91,7 +91,7 @@ static int rate_get_samples (struct audio_pcm_info *info, SpiceRateCtl *rate)
int64_t bytes; int64_t bytes;
int64_t samples; int64_t samples;
now = qemu_get_clock (vm_clock); now = qemu_get_clock_ns (vm_clock);
ticks = now - rate->start_ticks; ticks = now - rate->start_ticks;
bytes = muldiv64 (ticks, info->bytes_per_second, get_ticks_per_sec ()); bytes = muldiv64 (ticks, info->bytes_per_second, get_ticks_per_sec ());
samples = (bytes - rate->bytes_sent) >> info->shift; samples = (bytes - rate->bytes_sent) >> info->shift;

2
audio/wavaudio.c
View file

@ -52,7 +52,7 @@ static int wav_run_out (HWVoiceOut *hw, int live)
int rpos, decr, samples; int rpos, decr, samples;
uint8_t *dst; uint8_t *dst;
struct st_sample *src; struct st_sample *src;
int64_t now = qemu_get_clock (vm_clock); int64_t now = qemu_get_clock_ns (vm_clock);
int64_t ticks = now - wav->old_ticks; int64_t ticks = now - wav->old_ticks;
int64_t bytes = int64_t bytes =
muldiv64 (ticks, hw->info.bytes_per_second, get_ticks_per_sec ()); muldiv64 (ticks, hw->info.bytes_per_second, get_ticks_per_sec ());

6
buffered_file.c
View file

@ -238,7 +238,7 @@ static void buffered_rate_tick(void *opaque)
return; return;
} }
qemu_mod_timer(s->timer, qemu_get_clock(rt_clock) + 100); qemu_mod_timer(s->timer, qemu_get_clock_ms(rt_clock) + 100);
if (s->freeze_output) if (s->freeze_output)
return; return;
@ -274,9 +274,9 @@ QEMUFile *qemu_fopen_ops_buffered(void *opaque,
buffered_set_rate_limit, buffered_set_rate_limit,
buffered_get_rate_limit); buffered_get_rate_limit);
s->timer = qemu_new_timer(rt_clock, buffered_rate_tick, s); s->timer = qemu_new_timer_ms(rt_clock, buffered_rate_tick, s);
qemu_mod_timer(s->timer, qemu_get_clock(rt_clock) + 100); qemu_mod_timer(s->timer, qemu_get_clock_ms(rt_clock) + 100);
return s->file; return s->file;
} }

4
console.c
View file

@ -1135,7 +1135,7 @@ static void kbd_send_chars(void *opaque)
/* characters are pending: we send them a bit later (XXX: /* characters are pending: we send them a bit later (XXX:
horrible, should change char device API) */ horrible, should change char device API) */
if (s->out_fifo.count > 0) { if (s->out_fifo.count > 0) {
qemu_mod_timer(s->kbd_timer, qemu_get_clock(rt_clock) + 1); qemu_mod_timer(s->kbd_timer, qemu_get_clock_ms(rt_clock) + 1);
} }
} }
@ -1457,7 +1457,7 @@ static void text_console_do_init(CharDriverState *chr, DisplayState *ds)
s->out_fifo.buf = s->out_fifo_buf; s->out_fifo.buf = s->out_fifo_buf;
s->out_fifo.buf_size = sizeof(s->out_fifo_buf); s->out_fifo.buf_size = sizeof(s->out_fifo_buf);
s->kbd_timer = qemu_new_timer(rt_clock, kbd_send_chars, s); s->kbd_timer = qemu_new_timer_ms(rt_clock, kbd_send_chars, s);
s->ds = ds; s->ds = ds;
if (!color_inited) { if (!color_inited) {

8
hw/acpi_piix4.c
View file

@ -85,7 +85,7 @@ static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
static uint32_t get_pmtmr(PIIX4PMState *s) static uint32_t get_pmtmr(PIIX4PMState *s)
{ {
uint32_t d; uint32_t d;
d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec()); d = muldiv64(qemu_get_clock_ns(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
return d & 0xffffff; return d & 0xffffff;
} }
@ -93,7 +93,7 @@ static int get_pmsts(PIIX4PMState *s)
{ {
int64_t d; int64_t d;
d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, d = muldiv64(qemu_get_clock_ns(vm_clock), PM_TIMER_FREQUENCY,
get_ticks_per_sec()); get_ticks_per_sec());
if (d >= s->tmr_overflow_time) if (d >= s->tmr_overflow_time)
s->pmsts |= ACPI_BITMASK_TIMER_STATUS; s->pmsts |= ACPI_BITMASK_TIMER_STATUS;
@ -149,7 +149,7 @@ static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
pmsts = get_pmsts(s); pmsts = get_pmsts(s);
if (pmsts & val & ACPI_BITMASK_TIMER_STATUS) { if (pmsts & val & ACPI_BITMASK_TIMER_STATUS) {
/* if TMRSTS is reset, then compute the new overflow time */ /* if TMRSTS is reset, then compute the new overflow time */
d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, d = muldiv64(qemu_get_clock_ns(vm_clock), PM_TIMER_FREQUENCY,
get_ticks_per_sec()); get_ticks_per_sec());
s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL; s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
} }
@ -413,7 +413,7 @@ static int piix4_pm_initfn(PCIDevice *dev)
register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb); register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb); register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s); s->tmr_timer = qemu_new_timer_ns(vm_clock, pm_tmr_timer, s);
qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1); qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);

2
hw/adlib.c
View file

@ -166,7 +166,7 @@ static void timer_handler (int c, double interval_Sec)
s->ticking[n] = 1; s->ticking[n] = 1;
#ifdef DEBUG #ifdef DEBUG
interval = get_ticks_per_sec() * interval_Sec; interval = get_ticks_per_sec() * interval_Sec;
exp = qemu_get_clock (vm_clock) + interval; exp = qemu_get_clock_ns (vm_clock) + interval;
s->exp[n] = exp; s->exp[n] = exp;
#endif #endif

8
hw/apic.c
View file

@ -641,7 +641,7 @@ static uint32_t apic_get_current_count(APICState *s)
{ {
int64_t d; int64_t d;
uint32_t val; uint32_t val;
d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >> d = (qemu_get_clock_ns(vm_clock) - s->initial_count_load_time) >>
s->count_shift; s->count_shift;
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
/* periodic */ /* periodic */
@ -865,12 +865,12 @@ static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
int n = index - 0x32; int n = index - 0x32;
s->lvt[n] = val; s->lvt[n] = val;
if (n == APIC_LVT_TIMER) if (n == APIC_LVT_TIMER)
apic_timer_update(s, qemu_get_clock(vm_clock)); apic_timer_update(s, qemu_get_clock_ns(vm_clock));
} }
break; break;
case 0x38: case 0x38:
s->initial_count = val; s->initial_count = val;
s->initial_count_load_time = qemu_get_clock(vm_clock); s->initial_count_load_time = qemu_get_clock_ns(vm_clock);
apic_timer_update(s, s->initial_count_load_time); apic_timer_update(s, s->initial_count_load_time);
break; break;
case 0x39: case 0x39:
@ -1005,7 +1005,7 @@ static int apic_init1(SysBusDevice *dev)
DEVICE_NATIVE_ENDIAN); DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MSI_ADDR_SIZE, apic_io_memory); sysbus_init_mmio(dev, MSI_ADDR_SIZE, apic_io_memory);
s->timer = qemu_new_timer(vm_clock, apic_timer, s); s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s);
s->idx = last_apic_idx++; s->idx = last_apic_idx++;
local_apics[s->idx] = s; local_apics[s->idx] = s;
return 0; return 0;

2
hw/arm_sysctl.c
View file

@ -130,7 +130,7 @@ static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
case 0x58: /* BOOTCS */ case 0x58: /* BOOTCS */
return 0; return 0;
case 0x5c: /* 24MHz */ case 0x5c: /* 24MHz */
return muldiv64(qemu_get_clock(vm_clock), 24000000, get_ticks_per_sec()); return muldiv64(qemu_get_clock_ns(vm_clock), 24000000, get_ticks_per_sec());
case 0x60: /* MISC */ case 0x60: /* MISC */
return 0; return 0;
case 0x84: /* PROCID0 */ case 0x84: /* PROCID0 */

8
hw/armv7m_nvic.c
View file

@ -64,7 +64,7 @@ static inline int64_t systick_scale(nvic_state *s)
static void systick_reload(nvic_state *s, int reset) static void systick_reload(nvic_state *s, int reset)
{ {
if (reset) if (reset)
s->systick.tick = qemu_get_clock(vm_clock); s->systick.tick = qemu_get_clock_ns(vm_clock);
s->systick.tick += (s->systick.reload + 1) * systick_scale(s); s->systick.tick += (s->systick.reload + 1) * systick_scale(s);
qemu_mod_timer(s->systick.timer, s->systick.tick); qemu_mod_timer(s->systick.timer, s->systick.tick);
} }
@ -136,7 +136,7 @@ static uint32_t nvic_readl(void *opaque, uint32_t offset)
int64_t t; int64_t t;
if ((s->systick.control & SYSTICK_ENABLE) == 0) if ((s->systick.control & SYSTICK_ENABLE) == 0)
return 0; return 0;
t = qemu_get_clock(vm_clock); t = qemu_get_clock_ns(vm_clock);
if (t >= s->systick.tick) if (t >= s->systick.tick)
return 0; return 0;
val = ((s->systick.tick - (t + 1)) / systick_scale(s)) + 1; val = ((s->systick.tick - (t + 1)) / systick_scale(s)) + 1;
@ -273,7 +273,7 @@ static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
s->systick.control &= 0xfffffff8; s->systick.control &= 0xfffffff8;
s->systick.control |= value & 7; s->systick.control |= value & 7;
if ((oldval ^ value) & SYSTICK_ENABLE) { if ((oldval ^ value) & SYSTICK_ENABLE) {
int64_t now = qemu_get_clock(vm_clock); int64_t now = qemu_get_clock_ns(vm_clock);
if (value & SYSTICK_ENABLE) { if (value & SYSTICK_ENABLE) {
if (s->systick.tick) { if (s->systick.tick) {
s->systick.tick += now; s->systick.tick += now;
@ -396,7 +396,7 @@ static int armv7m_nvic_init(SysBusDevice *dev)
gic_init(&s->gic); gic_init(&s->gic);
cpu_register_physical_memory(0xe000e000, 0x1000, s->gic.iomemtype); cpu_register_physical_memory(0xe000e000, 0x1000, s->gic.iomemtype);
s->systick.timer = qemu_new_timer(vm_clock, systick_timer_tick, s); s->systick.timer = qemu_new_timer_ns(vm_clock, systick_timer_tick, s);
register_savevm(&dev->qdev, "armv7m_nvic", -1, 1, nvic_save, nvic_load, s); register_savevm(&dev->qdev, "armv7m_nvic", -1, 1, nvic_save, nvic_load, s);
return 0; return 0;
} }

4
hw/baum.c
View file

@ -335,7 +335,7 @@ static int baum_eat_packet(BaumDriverState *baum, const uint8_t *buf, int len)
int i; int i;
/* Allow 100ms to complete the DisplayData packet */ /* Allow 100ms to complete the DisplayData packet */
qemu_mod_timer(baum->cellCount_timer, qemu_get_clock(vm_clock) + qemu_mod_timer(baum->cellCount_timer, qemu_get_clock_ns(vm_clock) +
get_ticks_per_sec() / 10); get_ticks_per_sec() / 10);
for (i = 0; i < baum->x * baum->y ; i++) { for (i = 0; i < baum->x * baum->y ; i++) {
EAT(c); EAT(c);
@ -604,7 +604,7 @@ CharDriverState *chr_baum_init(QemuOpts *opts)
goto fail_handle; goto fail_handle;
} }
baum->cellCount_timer = qemu_new_timer(vm_clock, baum_cellCount_timer_cb, baum); baum->cellCount_timer = qemu_new_timer_ns(vm_clock, baum_cellCount_timer_cb, baum);
if (brlapi__getDisplaySize(handle, &baum->x, &baum->y) == -1) { if (brlapi__getDisplaySize(handle, &baum->x, &baum->y) == -1) {
brlapi_perror("baum_init: brlapi_getDisplaySize"); brlapi_perror("baum_init: brlapi_getDisplaySize");

4
hw/bt-hci-csr.c
View file

@ -88,7 +88,7 @@ static inline void csrhci_fifo_wake(struct csrhci_s *s)
} }
if (s->out_len) if (s->out_len)
qemu_mod_timer(s->out_tm, qemu_get_clock(vm_clock) + s->baud_delay); qemu_mod_timer(s->out_tm, qemu_get_clock_ns(vm_clock) + s->baud_delay);
} }
#define csrhci_out_packetz(s, len) memset(csrhci_out_packet(s, len), 0, len) #define csrhci_out_packetz(s, len) memset(csrhci_out_packet(s, len), 0, len)
@ -446,7 +446,7 @@ CharDriverState *uart_hci_init(qemu_irq wakeup)
s->hci->evt_recv = csrhci_out_hci_packet_event; s->hci->evt_recv = csrhci_out_hci_packet_event;
s->hci->acl_recv = csrhci_out_hci_packet_acl; s->hci->acl_recv = csrhci_out_hci_packet_acl;
s->out_tm = qemu_new_timer(vm_clock, csrhci_out_tick, s); s->out_tm = qemu_new_timer_ns(vm_clock, csrhci_out_tick, s);
s->pins = qemu_allocate_irqs(csrhci_pins, s, __csrhci_pins); s->pins = qemu_allocate_irqs(csrhci_pins, s, __csrhci_pins);
csrhci_reset(s); csrhci_reset(s);

12
hw/bt-hci.c
View file

@ -576,7 +576,7 @@ static void bt_hci_inquiry_result(struct bt_hci_s *hci,
static void bt_hci_mod_timer_1280ms(QEMUTimer *timer, int period) static void bt_hci_mod_timer_1280ms(QEMUTimer *timer, int period)
{ {
qemu_mod_timer(timer, qemu_get_clock(vm_clock) + qemu_mod_timer(timer, qemu_get_clock_ns(vm_clock) +
muldiv64(period << 7, get_ticks_per_sec(), 100)); muldiv64(period << 7, get_ticks_per_sec(), 100));
} }
@ -657,7 +657,7 @@ static void bt_hci_lmp_link_establish(struct bt_hci_s *hci,
if (master) { if (master) {
link->acl_mode = acl_active; link->acl_mode = acl_active;
hci->lm.handle[hci->lm.last_handle].acl_mode_timer = hci->lm.handle[hci->lm.last_handle].acl_mode_timer =
qemu_new_timer(vm_clock, bt_hci_mode_tick, link); qemu_new_timer_ns(vm_clock, bt_hci_mode_tick, link);
} }
} }
@ -1084,7 +1084,7 @@ static int bt_hci_mode_change(struct bt_hci_s *hci, uint16_t handle,
bt_hci_event_status(hci, HCI_SUCCESS); bt_hci_event_status(hci, HCI_SUCCESS);
qemu_mod_timer(link->acl_mode_timer, qemu_get_clock(vm_clock) + qemu_mod_timer(link->acl_mode_timer, qemu_get_clock_ns(vm_clock) +
muldiv64(interval * 625, get_ticks_per_sec(), 1000000)); muldiv64(interval * 625, get_ticks_per_sec(), 1000000));
bt_hci_lmp_mode_change_master(hci, link->link, mode, interval); bt_hci_lmp_mode_change_master(hci, link->link, mode, interval);
@ -2145,10 +2145,10 @@ struct HCIInfo *bt_new_hci(struct bt_scatternet_s *net)
{ {
struct bt_hci_s *s = qemu_mallocz(sizeof(struct bt_hci_s)); struct bt_hci_s *s = qemu_mallocz(sizeof(struct bt_hci_s));
s->lm.inquiry_done = qemu_new_timer(vm_clock, bt_hci_inquiry_done, s); s->lm.inquiry_done = qemu_new_timer_ns(vm_clock, bt_hci_inquiry_done, s);
s->lm.inquiry_next = qemu_new_timer(vm_clock, bt_hci_inquiry_next, s); s->lm.inquiry_next = qemu_new_timer_ns(vm_clock, bt_hci_inquiry_next, s);
s->conn_accept_timer = s->conn_accept_timer =
qemu_new_timer(vm_clock, bt_hci_conn_accept_timeout, s); qemu_new_timer_ns(vm_clock, bt_hci_conn_accept_timeout, s);
s->evt_packet = bt_hci_evt_packet; s->evt_packet = bt_hci_evt_packet;
s->evt_submit = bt_hci_evt_submit; s->evt_submit = bt_hci_evt_submit;

24
hw/cuda.c
View file

@ -170,7 +170,7 @@ static unsigned int get_counter(CUDATimer *s)
int64_t d; int64_t d;
unsigned int counter; unsigned int counter;
d = muldiv64(qemu_get_clock(vm_clock) - s->load_time, d = muldiv64(qemu_get_clock_ns(vm_clock) - s->load_time,
CUDA_TIMER_FREQ, get_ticks_per_sec()); CUDA_TIMER_FREQ, get_ticks_per_sec());
if (s->index == 0) { if (s->index == 0) {
/* the timer goes down from latch to -1 (period of latch + 2) */ /* the timer goes down from latch to -1 (period of latch + 2) */
@ -189,7 +189,7 @@ static unsigned int get_counter(CUDATimer *s)
static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val) static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val)
{ {
CUDA_DPRINTF("T%d.counter=%d\n", 1 + (ti->timer == NULL), val); CUDA_DPRINTF("T%d.counter=%d\n", 1 + (ti->timer == NULL), val);
ti->load_time = qemu_get_clock(vm_clock); ti->load_time = qemu_get_clock_ns(vm_clock);
ti->counter_value = val; ti->counter_value = val;
cuda_timer_update(s, ti, ti->load_time); cuda_timer_update(s, ti, ti->load_time);
} }
@ -346,7 +346,7 @@ static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
break; break;
case 4: case 4:
s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock)); cuda_timer_update(s, &s->timers[0], qemu_get_clock_ns(vm_clock));
break; break;
case 5: case 5:
s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
@ -355,12 +355,12 @@ static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
break; break;
case 6: case 6:
s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock)); cuda_timer_update(s, &s->timers[0], qemu_get_clock_ns(vm_clock));
break; break;
case 7: case 7:
s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
s->ifr &= ~T1_INT; s->ifr &= ~T1_INT;
cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock)); cuda_timer_update(s, &s->timers[0], qemu_get_clock_ns(vm_clock));
break; break;
case 8: case 8:
s->timers[1].latch = val; s->timers[1].latch = val;
@ -374,7 +374,7 @@ static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
break; break;
case 11: case 11:
s->acr = val; s->acr = val;
cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock)); cuda_timer_update(s, &s->timers[0], qemu_get_clock_ns(vm_clock));
cuda_update(s); cuda_update(s);
break; break;
case 12: case 12:
@ -506,7 +506,7 @@ static void cuda_adb_poll(void *opaque)
cuda_send_packet_to_host(s, obuf, olen + 2); cuda_send_packet_to_host(s, obuf, olen + 2);
} }
qemu_mod_timer(s->adb_poll_timer, qemu_mod_timer(s->adb_poll_timer,
qemu_get_clock(vm_clock) + qemu_get_clock_ns(vm_clock) +
(get_ticks_per_sec() / CUDA_ADB_POLL_FREQ)); (get_ticks_per_sec() / CUDA_ADB_POLL_FREQ));
} }
@ -524,7 +524,7 @@ static void cuda_receive_packet(CUDAState *s,
s->autopoll = autopoll; s->autopoll = autopoll;
if (autopoll) { if (autopoll) {
qemu_mod_timer(s->adb_poll_timer, qemu_mod_timer(s->adb_poll_timer,
qemu_get_clock(vm_clock) + qemu_get_clock_ns(vm_clock) +
(get_ticks_per_sec() / CUDA_ADB_POLL_FREQ)); (get_ticks_per_sec() / CUDA_ADB_POLL_FREQ));
} else { } else {
qemu_del_timer(s->adb_poll_timer); qemu_del_timer(s->adb_poll_timer);
@ -536,14 +536,14 @@ static void cuda_receive_packet(CUDAState *s,
break; break;
case CUDA_SET_TIME: case CUDA_SET_TIME:
ti = (((uint32_t)data[1]) << 24) + (((uint32_t)data[2]) << 16) + (((uint32_t)data[3]) << 8) + data[4]; ti = (((uint32_t)data[1]) << 24) + (((uint32_t)data[2]) << 16) + (((uint32_t)data[3]) << 8) + data[4];
s->tick_offset = ti - (qemu_get_clock(vm_clock) / get_ticks_per_sec()); s->tick_offset = ti - (qemu_get_clock_ns(vm_clock) / get_ticks_per_sec());
obuf[0] = CUDA_PACKET; obuf[0] = CUDA_PACKET;
obuf[1] = 0; obuf[1] = 0;
obuf[2] = 0; obuf[2] = 0;
cuda_send_packet_to_host(s, obuf, 3); cuda_send_packet_to_host(s, obuf, 3);
break; break;
case CUDA_GET_TIME: case CUDA_GET_TIME:
ti = s->tick_offset + (qemu_get_clock(vm_clock) / get_ticks_per_sec()); ti = s->tick_offset + (qemu_get_clock_ns(vm_clock) / get_ticks_per_sec());
obuf[0] = CUDA_PACKET; obuf[0] = CUDA_PACKET;
obuf[1] = 0; obuf[1] = 0;
obuf[2] = 0; obuf[2] = 0;
@ -754,14 +754,14 @@ void cuda_init (int *cuda_mem_index, qemu_irq irq)
s->irq = irq; s->irq = irq;
s->timers[0].index = 0; s->timers[0].index = 0;
s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s); s->timers[0].timer = qemu_new_timer_ns(vm_clock, cuda_timer1, s);
s->timers[1].index = 1; s->timers[1].index = 1;
qemu_get_timedate(&tm, 0); qemu_get_timedate(&tm, 0);
s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET; s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET;
s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s); s->adb_poll_timer = qemu_new_timer_ns(vm_clock, cuda_adb_poll, s);
*cuda_mem_index = cpu_register_io_memory(cuda_read, cuda_write, s, *cuda_mem_index = cpu_register_io_memory(cuda_read, cuda_write, s,
DEVICE_NATIVE_ENDIAN); DEVICE_NATIVE_ENDIAN);
register_savevm(NULL, "cuda", -1, 1, cuda_save, cuda_load, s); register_savevm(NULL, "cuda", -1, 1, cuda_save, cuda_load, s);

6
hw/dp8393x.c
View file

@ -290,7 +290,7 @@ static void set_next_tick(dp8393xState *s)
} }
ticks = s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0]; ticks = s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];
s->wt_last_update = qemu_get_clock(vm_clock); s->wt_last_update = qemu_get_clock_ns(vm_clock);
delay = get_ticks_per_sec() * ticks / 5000000; delay = get_ticks_per_sec() * ticks / 5000000;
qemu_mod_timer(s->watchdog, s->wt_last_update + delay); qemu_mod_timer(s->watchdog, s->wt_last_update + delay);
} }
@ -305,7 +305,7 @@ static void update_wt_regs(dp8393xState *s)
return; return;
} }
elapsed = s->wt_last_update - qemu_get_clock(vm_clock); elapsed = s->wt_last_update - qemu_get_clock_ns(vm_clock);
val = s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0]; val = s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];
val -= elapsed / 5000000; val -= elapsed / 5000000;
s->regs[SONIC_WT1] = (val >> 16) & 0xffff; s->regs[SONIC_WT1] = (val >> 16) & 0xffff;
@ -895,7 +895,7 @@ void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
s->memory_rw = memory_rw; s->memory_rw = memory_rw;
s->it_shift = it_shift; s->it_shift = it_shift;
s->irq = irq; s->irq = irq;
s->watchdog = qemu_new_timer(vm_clock, dp8393x_watchdog, s); s->watchdog = qemu_new_timer_ns(vm_clock, dp8393x_watchdog, s);
s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */ s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */
memcpy(s->conf.macaddr.a, nd->macaddr, sizeof(s->conf.macaddr)); memcpy(s->conf.macaddr.a, nd->macaddr, sizeof(s->conf.macaddr));

2
hw/etraxfs_timer.c
View file

@ -85,7 +85,7 @@ static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
r = ptimer_get_count(t->ptimer_t1); r = ptimer_get_count(t->ptimer_t1);
break; break;
case R_TIME: case R_TIME:
r = qemu_get_clock(vm_clock) / 10; r = qemu_get_clock_ns(vm_clock) / 10;
break; break;
case RW_INTR_MASK: case RW_INTR_MASK:
r = t->rw_intr_mask; r = t->rw_intr_mask;

4
hw/fdc.c
View file

@ -1423,7 +1423,7 @@ static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
/* XXX: should set main status register to busy */ /* XXX: should set main status register to busy */
cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
qemu_mod_timer(fdctrl->result_timer, qemu_mod_timer(fdctrl->result_timer,
qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 50)); qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 50));
} }
static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction) static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
@ -1830,7 +1830,7 @@ static int fdctrl_init_common(FDCtrl *fdctrl)
FLOPPY_DPRINTF("init controller\n"); FLOPPY_DPRINTF("init controller\n");
fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN); fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
fdctrl->fifo_size = 512; fdctrl->fifo_size = 512;
fdctrl->result_timer = qemu_new_timer(vm_clock, fdctrl->result_timer = qemu_new_timer_ns(vm_clock,
fdctrl_result_timer, fdctrl); fdctrl_result_timer, fdctrl);
fdctrl->version = 0x90; /* Intel 82078 controller */ fdctrl->version = 0x90; /* Intel 82078 controller */

14
hw/hpet.c
View file

@ -143,7 +143,7 @@ static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
static uint64_t hpet_get_ticks(HPETState *s) static uint64_t hpet_get_ticks(HPETState *s)
{ {
return ns_to_ticks(qemu_get_clock(vm_clock) + s->hpet_offset); return ns_to_ticks(qemu_get_clock_ns(vm_clock) + s->hpet_offset);
} }
/* /*
@ -224,7 +224,7 @@ static int hpet_post_load(void *opaque, int version_id)
HPETState *s = opaque; HPETState *s = opaque;
/* Recalculate the offset between the main counter and guest time */ /* Recalculate the offset between the main counter and guest time */
s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock); s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock_ns(vm_clock);
/* Push number of timers into capability returned via HPET_ID */ /* Push number of timers into capability returned via HPET_ID */
s->capability &= ~HPET_ID_NUM_TIM_MASK; s->capability &= ~HPET_ID_NUM_TIM_MASK;
@ -298,11 +298,11 @@ static void hpet_timer(void *opaque)
} }
diff = hpet_calculate_diff(t, cur_tick); diff = hpet_calculate_diff(t, cur_tick);
qemu_mod_timer(t->qemu_timer, qemu_mod_timer(t->qemu_timer,
qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff)); qemu_get_clock_ns(vm_clock) + (int64_t)ticks_to_ns(diff));
} else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) { } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
if (t->wrap_flag) { if (t->wrap_flag) {
diff = hpet_calculate_diff(t, cur_tick); diff = hpet_calculate_diff(t, cur_tick);
qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) + qemu_mod_timer(t->qemu_timer, qemu_get_clock_ns(vm_clock) +
(int64_t)ticks_to_ns(diff)); (int64_t)ticks_to_ns(diff));
t->wrap_flag = 0; t->wrap_flag = 0;
} }
@ -331,7 +331,7 @@ static void hpet_set_timer(HPETTimer *t)
} }
} }
qemu_mod_timer(t->qemu_timer, qemu_mod_timer(t->qemu_timer,
qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff)); qemu_get_clock_ns(vm_clock) + (int64_t)ticks_to_ns(diff));
} }
static void hpet_del_timer(HPETTimer *t) static void hpet_del_timer(HPETTimer *t)
@ -547,7 +547,7 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) { if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
/* Enable main counter and interrupt generation. */ /* Enable main counter and interrupt generation. */
s->hpet_offset = s->hpet_offset =
ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock); ticks_to_ns(s->hpet_counter) - qemu_get_clock_ns(vm_clock);
for (i = 0; i < s->num_timers; i++) { for (i = 0; i < s->num_timers; i++) {
if ((&s->timer[i])->cmp != ~0ULL) { if ((&s->timer[i])->cmp != ~0ULL) {
hpet_set_timer(&s->timer[i]); hpet_set_timer(&s->timer[i]);
@ -703,7 +703,7 @@ static int hpet_init(SysBusDevice *dev)
} }
for (i = 0; i < HPET_MAX_TIMERS; i++) { for (i = 0; i < HPET_MAX_TIMERS; i++) {
timer = &s->timer[i]; timer = &s->timer[i];
timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer); timer->qemu_timer = qemu_new_timer_ns(vm_clock, hpet_timer, timer);
timer->tn = i; timer->tn = i;
timer->state = s; timer->state = s;
} }

12
hw/i8254.c
View file

@ -69,7 +69,7 @@ static int pit_get_count(PITChannelState *s)
uint64_t d; uint64_t d;
int counter; int counter;
d = muldiv64(qemu_get_clock(vm_clock) - s->count_load_time, PIT_FREQ, d = muldiv64(qemu_get_clock_ns(vm_clock) - s->count_load_time, PIT_FREQ,
get_ticks_per_sec()); get_ticks_per_sec());
switch(s->mode) { switch(s->mode) {
case 0: case 0:
@ -198,7 +198,7 @@ void pit_set_gate(ISADevice *dev, int channel, int val)
case 5: case 5:
if (s->gate < val) { if (s->gate < val) {
/* restart counting on rising edge */ /* restart counting on rising edge */
s->count_load_time = qemu_get_clock(vm_clock); s->count_load_time = qemu_get_clock_ns(vm_clock);
pit_irq_timer_update(s, s->count_load_time); pit_irq_timer_update(s, s->count_load_time);
} }
break; break;
@ -206,7 +206,7 @@ void pit_set_gate(ISADevice *dev, int channel, int val)
case 3: case 3:
if (s->gate < val) { if (s->gate < val) {
/* restart counting on rising edge */ /* restart counting on rising edge */
s->count_load_time = qemu_get_clock(vm_clock); s->count_load_time = qemu_get_clock_ns(vm_clock);
pit_irq_timer_update(s, s->count_load_time); pit_irq_timer_update(s, s->count_load_time);
} }
/* XXX: disable/enable counting */ /* XXX: disable/enable counting */
@ -240,7 +240,7 @@ static inline void pit_load_count(PITChannelState *s, int val)
{ {
if (val == 0) if (val == 0)
val = 0x10000; val = 0x10000;
s->count_load_time = qemu_get_clock(vm_clock); s->count_load_time = qemu_get_clock_ns(vm_clock);
s->count = val; s->count = val;
pit_irq_timer_update(s, s->count_load_time); pit_irq_timer_update(s, s->count_load_time);
} }
@ -274,7 +274,7 @@ static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
if (!(val & 0x10) && !s->status_latched) { if (!(val & 0x10) && !s->status_latched) {
/* status latch */ /* status latch */
/* XXX: add BCD and null count */ /* XXX: add BCD and null count */
s->status = (pit_get_out1(s, qemu_get_clock(vm_clock)) << 7) | s->status = (pit_get_out1(s, qemu_get_clock_ns(vm_clock)) << 7) |
(s->rw_mode << 4) | (s->rw_mode << 4) |
(s->mode << 1) | (s->mode << 1) |
s->bcd; s->bcd;
@ -513,7 +513,7 @@ static int pit_initfn(ISADevice *dev)
s = &pit->channels[0]; s = &pit->channels[0];
/* the timer 0 is connected to an IRQ */ /* the timer 0 is connected to an IRQ */
s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s); s->irq_timer = qemu_new_timer_ns(vm_clock, pit_irq_timer, s);
s->irq = isa_get_irq(pit->irq); s->irq = isa_get_irq(pit->irq);
register_ioport_write(pit->iobase, 4, 1, pit_ioport_write, pit); register_ioport_write(pit->iobase, 4, 1, pit_ioport_write, pit);

4
hw/i8259.c
View file

@ -202,7 +202,7 @@ static void i8259_set_irq(void *opaque, int irq, int level)
#endif #endif
#ifdef DEBUG_IRQ_LATENCY #ifdef DEBUG_IRQ_LATENCY
if (level) { if (level) {
irq_time[irq] = qemu_get_clock(vm_clock); irq_time[irq] = qemu_get_clock_ns(vm_clock);
} }
#endif #endif
pic_set_irq1(&s->pics[irq >> 3], irq & 7, level); pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
@ -255,7 +255,7 @@ int pic_read_irq(PicState2 *s)
#ifdef DEBUG_IRQ_LATENCY #ifdef DEBUG_IRQ_LATENCY
printf("IRQ%d latency=%0.3fus\n", printf("IRQ%d latency=%0.3fus\n",
irq, irq,
(double)(qemu_get_clock(vm_clock) - (double)(qemu_get_clock_ns(vm_clock) -
irq_time[irq]) * 1000000.0 / get_ticks_per_sec()); irq_time[irq]) * 1000000.0 / get_ticks_per_sec());
#endif #endif
DPRINTF("pic_interrupt: irq=%d\n", irq); DPRINTF("pic_interrupt: irq=%d\n", irq);

4
hw/ide/core.c
View file

@ -611,7 +611,7 @@ void ide_sector_write(IDEState *s)
option _only_ to install Windows 2000. You must disable it option _only_ to install Windows 2000. You must disable it
for normal use. */ for normal use. */
qemu_mod_timer(s->sector_write_timer, qemu_mod_timer(s->sector_write_timer,
qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 1000)); qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 1000));
} else { } else {
ide_set_irq(s->bus); ide_set_irq(s->bus);
} }
@ -2585,7 +2585,7 @@ static void ide_init1(IDEBus *bus, int unit)
s->io_buffer = qemu_memalign(2048, IDE_DMA_BUF_SECTORS*512 + 4); s->io_buffer = qemu_memalign(2048, IDE_DMA_BUF_SECTORS*512 + 4);
s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4; s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
s->smart_selftest_data = qemu_blockalign(s->bs, 512); s->smart_selftest_data = qemu_blockalign(s->bs, 512);
s->sector_write_timer = qemu_new_timer(vm_clock, s->sector_write_timer = qemu_new_timer_ns(vm_clock,
ide_sector_write_timer_cb, s); ide_sector_write_timer_cb, s);
} }

2
hw/intel-hda.c
View file

@ -1126,7 +1126,7 @@ static void intel_hda_reset(DeviceState *dev)
HDACodecDevice *cdev; HDACodecDevice *cdev;
intel_hda_regs_reset(d); intel_hda_regs_reset(d);
d->wall_base_ns = qemu_get_clock(vm_clock); d->wall_base_ns = qemu_get_clock_ns(vm_clock);
/* reset codecs */ /* reset codecs */
QLIST_FOREACH(qdev, &d->codecs.qbus.children, sibling) { QLIST_FOREACH(qdev, &d->codecs.qbus.children, sibling) {

4
hw/lan9118.c
View file

@ -327,7 +327,7 @@ static void lan9118_reset(DeviceState *d)
s->afc_cfg = 0; s->afc_cfg = 0;
s->e2p_cmd = 0; s->e2p_cmd = 0;
s->e2p_data = 0; s->e2p_data = 0;
s->free_timer_start = qemu_get_clock(vm_clock) / 40; s->free_timer_start = qemu_get_clock_ns(vm_clock) / 40;
ptimer_stop(s->timer); ptimer_stop(s->timer);
ptimer_set_count(s->timer, 0xffff); ptimer_set_count(s->timer, 0xffff);
@ -1070,7 +1070,7 @@ static uint32_t lan9118_readl(void *opaque, target_phys_addr_t offset)
case CSR_WORD_SWAP: case CSR_WORD_SWAP:
return s->word_swap; return s->word_swap;
case CSR_FREE_RUN: case CSR_FREE_RUN:
return (qemu_get_clock(vm_clock) / 40) - s->free_timer_start; return (qemu_get_clock_ns(vm_clock) / 40) - s->free_timer_start;
case CSR_RX_DROP: case CSR_RX_DROP:
/* TODO: Implement dropped frames counter. */ /* TODO: Implement dropped frames counter. */
return 0; return 0;

6
hw/lm832x.c
View file

@ -463,9 +463,9 @@ static int lm8323_init(i2c_slave *i2c)
LM823KbdState *s = FROM_I2C_SLAVE(LM823KbdState, i2c); LM823KbdState *s = FROM_I2C_SLAVE(LM823KbdState, i2c);
s->model = 0x8323; s->model = 0x8323;
s->pwm.tm[0] = qemu_new_timer(vm_clock, lm_kbd_pwm0_tick, s); s->pwm.tm[0] = qemu_new_timer_ns(vm_clock, lm_kbd_pwm0_tick, s);
s->pwm.tm[1] = qemu_new_timer(vm_clock, lm_kbd_pwm1_tick, s); s->pwm.tm[1] = qemu_new_timer_ns(vm_clock, lm_kbd_pwm1_tick, s);
s->pwm.tm[2] = qemu_new_timer(vm_clock, lm_kbd_pwm2_tick, s); s->pwm.tm[2] = qemu_new_timer_ns(vm_clock, lm_kbd_pwm2_tick, s);
qdev_init_gpio_out(&i2c->qdev, &s->nirq, 1); qdev_init_gpio_out(&i2c->qdev, &s->nirq, 1);
lm_kbd_reset(s); lm_kbd_reset(s);

6
hw/m48t59.c
View file

@ -123,7 +123,7 @@ static void alarm_cb (void *opaque)
/* Repeat once a second */ /* Repeat once a second */
next_time = 1; next_time = 1;
} }
qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock(vm_clock) + qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock_ns(vm_clock) +
next_time * 1000); next_time * 1000);
qemu_set_irq(NVRAM->IRQ, 0); qemu_set_irq(NVRAM->IRQ, 0);
} }
@ -691,8 +691,8 @@ static void m48t59_init_common(M48t59State *s)
{ {
s->buffer = qemu_mallocz(s->size); s->buffer = qemu_mallocz(s->size);
if (s->type == 59) { if (s->type == 59) {
s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s); s->alrm_timer = qemu_new_timer_ns(vm_clock, &alarm_cb, s);
s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s); s->wd_timer = qemu_new_timer_ns(vm_clock, &watchdog_cb, s);
} }
qemu_get_timedate(&s->alarm, 0); qemu_get_timedate(&s->alarm, 0);

16
hw/mc146818rtc.c
View file

@ -112,7 +112,7 @@ static void rtc_coalesced_timer_update(RTCState *s)
} else { } else {
/* divide each RTC interval to 2 - 8 smaller intervals */ /* divide each RTC interval to 2 - 8 smaller intervals */
int c = MIN(s->irq_coalesced, 7) + 1; int c = MIN(s->irq_coalesced, 7) + 1;
int64_t next_clock = qemu_get_clock(rtc_clock) + int64_t next_clock = qemu_get_clock_ns(rtc_clock) +
muldiv64(s->period / c, get_ticks_per_sec(), 32768); muldiv64(s->period / c, get_ticks_per_sec(), 32768);
qemu_mod_timer(s->coalesced_timer, next_clock); qemu_mod_timer(s->coalesced_timer, next_clock);
} }
@ -234,7 +234,7 @@ static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
/* UIP bit is read only */ /* UIP bit is read only */
s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
(s->cmos_data[RTC_REG_A] & REG_A_UIP); (s->cmos_data[RTC_REG_A] & REG_A_UIP);
rtc_timer_update(s, qemu_get_clock(rtc_clock)); rtc_timer_update(s, qemu_get_clock_ns(rtc_clock));
break; break;
case RTC_REG_B: case RTC_REG_B:
if (data & REG_B_SET) { if (data & REG_B_SET) {
@ -256,7 +256,7 @@ static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
} else { } else {
s->cmos_data[RTC_REG_B] = data; s->cmos_data[RTC_REG_B] = data;
} }
rtc_timer_update(s, qemu_get_clock(rtc_clock)); rtc_timer_update(s, qemu_get_clock_ns(rtc_clock));
break; break;
case RTC_REG_C: case RTC_REG_C:
case RTC_REG_D: case RTC_REG_D:
@ -599,17 +599,17 @@ static int rtc_initfn(ISADevice *dev)
rtc_set_date_from_host(dev); rtc_set_date_from_host(dev);
s->periodic_timer = qemu_new_timer(rtc_clock, rtc_periodic_timer, s); s->periodic_timer = qemu_new_timer_ns(rtc_clock, rtc_periodic_timer, s);
#ifdef TARGET_I386 #ifdef TARGET_I386
if (rtc_td_hack) if (rtc_td_hack)
s->coalesced_timer = s->coalesced_timer =
qemu_new_timer(rtc_clock, rtc_coalesced_timer, s); qemu_new_timer_ns(rtc_clock, rtc_coalesced_timer, s);
#endif #endif
s->second_timer = qemu_new_timer(rtc_clock, rtc_update_second, s); s->second_timer = qemu_new_timer_ns(rtc_clock, rtc_update_second, s);
s->second_timer2 = qemu_new_timer(rtc_clock, rtc_update_second2, s); s->second_timer2 = qemu_new_timer_ns(rtc_clock, rtc_update_second2, s);
s->next_second_time = s->next_second_time =
qemu_get_clock(rtc_clock) + (get_ticks_per_sec() * 99) / 100; qemu_get_clock_ns(rtc_clock) + (get_ticks_per_sec() * 99) / 100;
qemu_mod_timer(s->second_timer2, s->next_second_time); qemu_mod_timer(s->second_timer2, s->next_second_time);
register_ioport_write(base, 2, 1, cmos_ioport_write, s); register_ioport_write(base, 2, 1, cmos_ioport_write, s);

10
hw/mips_timer.c
View file

@ -47,7 +47,7 @@ static void cpu_mips_timer_update(CPUState *env)
uint64_t now, next; uint64_t now, next;
uint32_t wait; uint32_t wait;
now = qemu_get_clock(vm_clock); now = qemu_get_clock_ns(vm_clock);
wait = env->CP0_Compare - env->CP0_Count - wait = env->CP0_Compare - env->CP0_Count -
(uint32_t)muldiv64(now, TIMER_FREQ, get_ticks_per_sec()); (uint32_t)muldiv64(now, TIMER_FREQ, get_ticks_per_sec());
next = now + muldiv64(wait, get_ticks_per_sec(), TIMER_FREQ); next = now + muldiv64(wait, get_ticks_per_sec(), TIMER_FREQ);
@ -71,7 +71,7 @@ uint32_t cpu_mips_get_count (CPUState *env)
} else { } else {
uint64_t now; uint64_t now;
now = qemu_get_clock(vm_clock); now = qemu_get_clock_ns(vm_clock);
if (qemu_timer_pending(env->timer) if (qemu_timer_pending(env->timer)
&& qemu_timer_expired(env->timer, now)) { && qemu_timer_expired(env->timer, now)) {
/* The timer has already expired. */ /* The timer has already expired. */
@ -90,7 +90,7 @@ void cpu_mips_store_count (CPUState *env, uint32_t count)
else { else {
/* Store new count register */ /* Store new count register */
env->CP0_Count = env->CP0_Count =
count - (uint32_t)muldiv64(qemu_get_clock(vm_clock), count - (uint32_t)muldiv64(qemu_get_clock_ns(vm_clock),
TIMER_FREQ, get_ticks_per_sec()); TIMER_FREQ, get_ticks_per_sec());
/* Update timer timer */ /* Update timer timer */
cpu_mips_timer_update(env); cpu_mips_timer_update(env);
@ -115,7 +115,7 @@ void cpu_mips_start_count(CPUState *env)
void cpu_mips_stop_count(CPUState *env) void cpu_mips_stop_count(CPUState *env)
{ {
/* Store the current value */ /* Store the current value */
env->CP0_Count += (uint32_t)muldiv64(qemu_get_clock(vm_clock), env->CP0_Count += (uint32_t)muldiv64(qemu_get_clock_ns(vm_clock),
TIMER_FREQ, get_ticks_per_sec()); TIMER_FREQ, get_ticks_per_sec());
} }
@ -141,7 +141,7 @@ static void mips_timer_cb (void *opaque)
void cpu_mips_clock_init (CPUState *env) void cpu_mips_clock_init (CPUState *env)
{ {
env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env); env->timer = qemu_new_timer_ns(vm_clock, &mips_timer_cb, env);
env->CP0_Compare = 0; env->CP0_Compare = 0;
cpu_mips_store_count(env, 1); cpu_mips_store_count(env, 1);
} }

6
hw/mpcore.c
View file

@ -63,7 +63,7 @@ static void mpcore_timer_reload(mpcore_timer_state *s, int restart)
if (s->count == 0) if (s->count == 0)
return; return;
if (restart) if (restart)
s->tick = qemu_get_clock(vm_clock); s->tick = qemu_get_clock_ns(vm_clock);
s->tick += (int64_t)s->count * mpcore_timer_scale(s); s->tick += (int64_t)s->count * mpcore_timer_scale(s);
qemu_mod_timer(s->timer, s->tick); qemu_mod_timer(s->timer, s->tick);
} }
@ -92,7 +92,7 @@ static uint32_t mpcore_timer_read(mpcore_timer_state *s, int offset)
if (((s->control & 1) == 0) || (s->count == 0)) if (((s->control & 1) == 0) || (s->count == 0))
return 0; return 0;
/* Slow and ugly, but hopefully won't happen too often. */ /* Slow and ugly, but hopefully won't happen too often. */
val = s->tick - qemu_get_clock(vm_clock); val = s->tick - qemu_get_clock_ns(vm_clock);
val /= mpcore_timer_scale(s); val /= mpcore_timer_scale(s);
if (val < 0) if (val < 0)
val = 0; val = 0;
@ -145,7 +145,7 @@ static void mpcore_timer_init(mpcore_priv_state *mpcore,
{ {
s->id = id; s->id = id;
s->mpcore = mpcore; s->mpcore = mpcore;
s->timer = qemu_new_timer(vm_clock, mpcore_timer_tick, s); s->timer = qemu_new_timer_ns(vm_clock, mpcore_timer_tick, s);
} }

30
hw/omap1.c
View file

@ -101,7 +101,7 @@ struct omap_mpu_timer_s {
static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer) static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer)
{ {
uint64_t distance = qemu_get_clock(vm_clock) - timer->time; uint64_t distance = qemu_get_clock_ns(vm_clock) - timer->time;
if (timer->st && timer->enable && timer->rate) if (timer->st && timer->enable && timer->rate)
return timer->val - muldiv64(distance >> (timer->ptv + 1), return timer->val - muldiv64(distance >> (timer->ptv + 1),
@ -113,7 +113,7 @@ static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer)
static inline void omap_timer_sync(struct omap_mpu_timer_s *timer) static inline void omap_timer_sync(struct omap_mpu_timer_s *timer)
{ {
timer->val = omap_timer_read(timer); timer->val = omap_timer_read(timer);
timer->time = qemu_get_clock(vm_clock); timer->time = qemu_get_clock_ns(vm_clock);
} }
static inline void omap_timer_update(struct omap_mpu_timer_s *timer) static inline void omap_timer_update(struct omap_mpu_timer_s *timer)
@ -258,7 +258,7 @@ static struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
s->irq = irq; s->irq = irq;
s->clk = clk; s->clk = clk;
s->timer = qemu_new_timer(vm_clock, omap_timer_tick, s); s->timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, s);
s->tick = qemu_bh_new(omap_timer_fire, s); s->tick = qemu_bh_new(omap_timer_fire, s);
omap_mpu_timer_reset(s); omap_mpu_timer_reset(s);
omap_timer_clk_setup(s); omap_timer_clk_setup(s);
@ -382,7 +382,7 @@ static struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
s->timer.irq = irq; s->timer.irq = irq;
s->timer.clk = clk; s->timer.clk = clk;
s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer); s->timer.timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, &s->timer);
omap_wd_timer_reset(s); omap_wd_timer_reset(s);
omap_timer_clk_setup(&s->timer); omap_timer_clk_setup(&s->timer);
@ -484,7 +484,7 @@ static struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
s->timer.irq = irq; s->timer.irq = irq;
s->timer.clk = clk; s->timer.clk = clk;
s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer); s->timer.timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, &s->timer);
omap_os_timer_reset(s); omap_os_timer_reset(s);
omap_timer_clk_setup(&s->timer); omap_timer_clk_setup(&s->timer);
@ -580,7 +580,7 @@ static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
case 0x10: /* GAUGING_CTRL */ case 0x10: /* GAUGING_CTRL */
/* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */ /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) { if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) {
now = qemu_get_clock(vm_clock); now = qemu_get_clock_ns(vm_clock);
if (value & 1) if (value & 1)
s->ulpd_gauge_start = now; s->ulpd_gauge_start = now;
@ -2802,7 +2802,7 @@ static void omap_rtc_reset(struct omap_rtc_s *s)
s->pm_am = 0; s->pm_am = 0;
s->auto_comp = 0; s->auto_comp = 0;
s->round = 0; s->round = 0;
s->tick = qemu_get_clock(rt_clock); s->tick = qemu_get_clock_ms(rt_clock);
memset(&s->alarm_tm, 0, sizeof(s->alarm_tm)); memset(&s->alarm_tm, 0, sizeof(s->alarm_tm));
s->alarm_tm.tm_mday = 0x01; s->alarm_tm.tm_mday = 0x01;
s->status = 1 << 7; s->status = 1 << 7;
@ -2822,7 +2822,7 @@ static struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
s->irq = irq[0]; s->irq = irq[0];
s->alarm = irq[1]; s->alarm = irq[1];
s->clk = qemu_new_timer(rt_clock, omap_rtc_tick, s); s->clk = qemu_new_timer_ms(rt_clock, omap_rtc_tick, s);
omap_rtc_reset(s); omap_rtc_reset(s);
@ -2915,7 +2915,7 @@ static void omap_mcbsp_source_tick(void *opaque)
s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7]; s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7];
omap_mcbsp_rx_newdata(s); omap_mcbsp_rx_newdata(s);
qemu_mod_timer(s->source_timer, qemu_get_clock(vm_clock) + qemu_mod_timer(s->source_timer, qemu_get_clock_ns(vm_clock) +
get_ticks_per_sec()); get_ticks_per_sec());
} }
@ -2961,7 +2961,7 @@ static void omap_mcbsp_sink_tick(void *opaque)
s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7]; s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7];
omap_mcbsp_tx_newdata(s); omap_mcbsp_tx_newdata(s);
qemu_mod_timer(s->sink_timer, qemu_get_clock(vm_clock) + qemu_mod_timer(s->sink_timer, qemu_get_clock_ns(vm_clock) +
get_ticks_per_sec()); get_ticks_per_sec());
} }
@ -3344,8 +3344,8 @@ struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
s->rxirq = irq[1]; s->rxirq = irq[1];
s->txdrq = dma[0]; s->txdrq = dma[0];
s->rxdrq = dma[1]; s->rxdrq = dma[1];
s->sink_timer = qemu_new_timer(vm_clock, omap_mcbsp_sink_tick, s); s->sink_timer = qemu_new_timer_ns(vm_clock, omap_mcbsp_sink_tick, s);
s->source_timer = qemu_new_timer(vm_clock, omap_mcbsp_source_tick, s); s->source_timer = qemu_new_timer_ns(vm_clock, omap_mcbsp_source_tick, s);
omap_mcbsp_reset(s); omap_mcbsp_reset(s);
iomemtype = cpu_register_io_memory(omap_mcbsp_readfn, iomemtype = cpu_register_io_memory(omap_mcbsp_readfn,
@ -3399,9 +3399,9 @@ static void omap_lpg_tick(void *opaque)
struct omap_lpg_s *s = opaque; struct omap_lpg_s *s = opaque;
if (s->cycle) if (s->cycle)
qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->period - s->on); qemu_mod_timer(s->tm, qemu_get_clock_ms(rt_clock) + s->period - s->on);
else else
qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->on); qemu_mod_timer(s->tm, qemu_get_clock_ms(rt_clock) + s->on);
s->cycle = !s->cycle; s->cycle = !s->cycle;
printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off"); printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off");
@ -3516,7 +3516,7 @@ static struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
struct omap_lpg_s *s = (struct omap_lpg_s *) struct omap_lpg_s *s = (struct omap_lpg_s *)
qemu_mallocz(sizeof(struct omap_lpg_s)); qemu_mallocz(sizeof(struct omap_lpg_s));
s->tm = qemu_new_timer(rt_clock, omap_lpg_tick, s); s->tm = qemu_new_timer_ms(rt_clock, omap_lpg_tick, s);
omap_lpg_reset(s); omap_lpg_reset(s);

14
hw/omap_gptimer.c
View file

@ -102,7 +102,7 @@ static inline uint32_t omap_gp_timer_read(struct omap_gp_timer_s *timer)
uint64_t distance; uint64_t distance;
if (timer->st && timer->rate) { if (timer->st && timer->rate) {
distance = qemu_get_clock(vm_clock) - timer->time; distance = qemu_get_clock_ns(vm_clock) - timer->time;
distance = muldiv64(distance, timer->rate, timer->ticks_per_sec); distance = muldiv64(distance, timer->rate, timer->ticks_per_sec);
if (distance >= 0xffffffff - timer->val) if (distance >= 0xffffffff - timer->val)
@ -117,7 +117,7 @@ static inline void omap_gp_timer_sync(struct omap_gp_timer_s *timer)
{ {
if (timer->st) { if (timer->st) {
timer->val = omap_gp_timer_read(timer); timer->val = omap_gp_timer_read(timer);
timer->time = qemu_get_clock(vm_clock); timer->time = qemu_get_clock_ns(vm_clock);
} }
} }
@ -163,7 +163,7 @@ static void omap_gp_timer_tick(void *opaque)
timer->val = 0; timer->val = 0;
} else { } else {
timer->val = timer->load_val; timer->val = timer->load_val;
timer->time = qemu_get_clock(vm_clock); timer->time = qemu_get_clock_ns(vm_clock);
} }
if (timer->trigger == gpt_trigger_overflow || if (timer->trigger == gpt_trigger_overflow ||
@ -411,7 +411,7 @@ static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr,
break; break;
case 0x28: /* TCRR */ case 0x28: /* TCRR */
s->time = qemu_get_clock(vm_clock); s->time = qemu_get_clock_ns(vm_clock);
s->val = value; s->val = value;
omap_gp_timer_update(s); omap_gp_timer_update(s);
break; break;
@ -421,7 +421,7 @@ static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr,
break; break;
case 0x30: /* TTGR */ case 0x30: /* TTGR */
s->time = qemu_get_clock(vm_clock); s->time = qemu_get_clock_ns(vm_clock);
s->val = s->load_val; s->val = s->load_val;
omap_gp_timer_update(s); omap_gp_timer_update(s);
break; break;
@ -470,8 +470,8 @@ struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
s->ta = ta; s->ta = ta;
s->irq = irq; s->irq = irq;
s->clk = fclk; s->clk = fclk;
s->timer = qemu_new_timer(vm_clock, omap_gp_timer_tick, s); s->timer = qemu_new_timer_ns(vm_clock, omap_gp_timer_tick, s);
s->match = qemu_new_timer(vm_clock, omap_gp_timer_match, s); s->match = qemu_new_timer_ns(vm_clock, omap_gp_timer_match, s);
s->in = qemu_allocate_irqs(omap_gp_timer_input, s, 1)[0]; s->in = qemu_allocate_irqs(omap_gp_timer_input, s, 1)[0];
omap_gp_timer_reset(s); omap_gp_timer_reset(s);
omap_gp_timer_clk_setup(s); omap_gp_timer_clk_setup(s);

2
hw/omap_synctimer.c
View file

@ -27,7 +27,7 @@ struct omap_synctimer_s {
/* 32-kHz Sync Timer of the OMAP2 */ /* 32-kHz Sync Timer of the OMAP2 */
static uint32_t omap_synctimer_read(struct omap_synctimer_s *s) { static uint32_t omap_synctimer_read(struct omap_synctimer_s *s) {
return muldiv64(qemu_get_clock(vm_clock), 0x8000, get_ticks_per_sec()); return muldiv64(qemu_get_clock_ns(vm_clock), 0x8000, get_ticks_per_sec());
} }
void omap_synctimer_reset(struct omap_synctimer_s *s) void omap_synctimer_reset(struct omap_synctimer_s *s)

6
hw/pcnet.c
View file

@ -1336,7 +1336,7 @@ static void pcnet_poll_timer(void *opaque)
pcnet_update_irq(s); pcnet_update_irq(s);
if (!CSR_STOP(s) && !CSR_SPND(s) && !CSR_DPOLL(s)) { if (!CSR_STOP(s) && !CSR_SPND(s) && !CSR_DPOLL(s)) {
uint64_t now = qemu_get_clock(vm_clock) * 33; uint64_t now = qemu_get_clock_ns(vm_clock) * 33;
if (!s->timer || !now) if (!s->timer || !now)
s->timer = now; s->timer = now;
else { else {
@ -1348,7 +1348,7 @@ static void pcnet_poll_timer(void *opaque)
CSR_POLL(s) = t; CSR_POLL(s) = t;
} }
qemu_mod_timer(s->poll_timer, qemu_mod_timer(s->poll_timer,
pcnet_get_next_poll_time(s,qemu_get_clock(vm_clock))); pcnet_get_next_poll_time(s,qemu_get_clock_ns(vm_clock)));
} }
} }
@ -1726,7 +1726,7 @@ int pcnet_common_init(DeviceState *dev, PCNetState *s, NetClientInfo *info)
int i; int i;
uint16_t checksum; uint16_t checksum;
s->poll_timer = qemu_new_timer(vm_clock, pcnet_poll_timer, s); s->poll_timer = qemu_new_timer_ns(vm_clock, pcnet_poll_timer, s);
qemu_macaddr_default_if_unset(&s->conf.macaddr); qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(info, &s->conf, dev->info->name, dev->id, s); s->nic = qemu_new_nic(info, &s->conf, dev->info->name, dev->id, s);

2
hw/pcspk.c
View file

@ -118,7 +118,7 @@ static uint32_t pcspk_ioport_read(void *opaque, uint32_t addr)
int out; int out;
s->dummy_refresh_clock ^= (1 << 4); s->dummy_refresh_clock ^= (1 << 4);
out = pit_get_out(s->pit, 2, qemu_get_clock(vm_clock)) << 5; out = pit_get_out(s->pit, 2, qemu_get_clock_ns(vm_clock)) << 5;
return pit_get_gate(s->pit, 2) | (s->data_on << 1) | s->dummy_refresh_clock | out; return pit_get_gate(s->pit, 2) | (s->data_on << 1) | s->dummy_refresh_clock | out;
} }

2
hw/pflash_cfi01.c
View file

@ -628,7 +628,7 @@ pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
#else #else
pfl->ro = 0; pfl->ro = 0;
#endif #endif
pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl); pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl);
pfl->base = base; pfl->base = base;
pfl->sector_len = sector_len; pfl->sector_len = sector_len;
pfl->total_len = total_len; pfl->total_len = total_len;

6
hw/pflash_cfi02.c
View file

@ -390,7 +390,7 @@ static void pflash_write (pflash_t *pfl, target_phys_addr_t offset,
pflash_update(pfl, 0, pfl->chip_len); pflash_update(pfl, 0, pfl->chip_len);
/* Let's wait 5 seconds before chip erase is done */ /* Let's wait 5 seconds before chip erase is done */
qemu_mod_timer(pfl->timer, qemu_mod_timer(pfl->timer,
qemu_get_clock(vm_clock) + (get_ticks_per_sec() * 5)); qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() * 5));
break; break;
case 0x30: case 0x30:
/* Sector erase */ /* Sector erase */
@ -403,7 +403,7 @@ static void pflash_write (pflash_t *pfl, target_phys_addr_t offset,
pfl->status = 0x00; pfl->status = 0x00;
/* Let's wait 1/2 second before sector erase is done */ /* Let's wait 1/2 second before sector erase is done */
qemu_mod_timer(pfl->timer, qemu_mod_timer(pfl->timer,
qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 2)); qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 2));
break; break;
default: default:
DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd); DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
@ -647,7 +647,7 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
#else #else
pfl->ro = 0; pfl->ro = 0;
#endif #endif
pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl); pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl);
pfl->sector_len = sector_len; pfl->sector_len = sector_len;
pfl->width = width; pfl->width = width;
pfl->wcycle = 0; pfl->wcycle = 0;

8
hw/pl031.c
View file

@ -80,9 +80,9 @@ static void pl031_interrupt(void * opaque)
static uint32_t pl031_get_count(pl031_state *s) static uint32_t pl031_get_count(pl031_state *s)
{ {
/* This assumes qemu_get_clock returns the time since the machine was /* This assumes qemu_get_clock_ns returns the time since the machine was
created. */ created. */
return s->tick_offset + qemu_get_clock(vm_clock) / get_ticks_per_sec(); return s->tick_offset + qemu_get_clock_ns(vm_clock) / get_ticks_per_sec();
} }
static void pl031_set_alarm(pl031_state *s) static void pl031_set_alarm(pl031_state *s)
@ -90,7 +90,7 @@ static void pl031_set_alarm(pl031_state *s)
int64_t now; int64_t now;
uint32_t ticks; uint32_t ticks;
now = qemu_get_clock(vm_clock); now = qemu_get_clock_ns(vm_clock);
ticks = s->tick_offset + now / get_ticks_per_sec(); ticks = s->tick_offset + now / get_ticks_per_sec();
/* The timer wraps around. This subtraction also wraps in the same way, /* The timer wraps around. This subtraction also wraps in the same way,
@ -217,7 +217,7 @@ static int pl031_init(SysBusDevice *dev)
qemu_get_timedate(&tm, 0); qemu_get_timedate(&tm, 0);
s->tick_offset = mktimegm(&tm); s->tick_offset = mktimegm(&tm);
s->timer = qemu_new_timer(vm_clock, pl031_interrupt, s); s->timer = qemu_new_timer_ns(vm_clock, pl031_interrupt, s);
return 0; return 0;
} }

52
hw/ppc.c
View file

@ -419,7 +419,7 @@ uint64_t cpu_ppc_load_tbl (CPUState *env)
ppc_tb_t *tb_env = env->tb_env; ppc_tb_t *tb_env = env->tb_env;
uint64_t tb; uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset);
LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
return tb; return tb;
@ -430,7 +430,7 @@ static inline uint32_t _cpu_ppc_load_tbu(CPUState *env)
ppc_tb_t *tb_env = env->tb_env; ppc_tb_t *tb_env = env->tb_env;
uint64_t tb; uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset);
LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
return tb >> 32; return tb >> 32;
@ -454,9 +454,9 @@ void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
ppc_tb_t *tb_env = env->tb_env; ppc_tb_t *tb_env = env->tb_env;
uint64_t tb; uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset);
tb &= 0xFFFFFFFF00000000ULL; tb &= 0xFFFFFFFF00000000ULL;
cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock),
&tb_env->tb_offset, tb | (uint64_t)value); &tb_env->tb_offset, tb | (uint64_t)value);
} }
@ -465,9 +465,9 @@ static inline void _cpu_ppc_store_tbu(CPUState *env, uint32_t value)
ppc_tb_t *tb_env = env->tb_env; ppc_tb_t *tb_env = env->tb_env;
uint64_t tb; uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset);
tb &= 0x00000000FFFFFFFFULL; tb &= 0x00000000FFFFFFFFULL;
cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock),
&tb_env->tb_offset, ((uint64_t)value << 32) | tb); &tb_env->tb_offset, ((uint64_t)value << 32) | tb);
} }
@ -481,7 +481,7 @@ uint64_t cpu_ppc_load_atbl (CPUState *env)
ppc_tb_t *tb_env = env->tb_env; ppc_tb_t *tb_env = env->tb_env;
uint64_t tb; uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset);
LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
return tb; return tb;
@ -492,7 +492,7 @@ uint32_t cpu_ppc_load_atbu (CPUState *env)
ppc_tb_t *tb_env = env->tb_env; ppc_tb_t *tb_env = env->tb_env;
uint64_t tb; uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset);
LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
return tb >> 32; return tb >> 32;
@ -503,9 +503,9 @@ void cpu_ppc_store_atbl (CPUState *env, uint32_t value)
ppc_tb_t *tb_env = env->tb_env; ppc_tb_t *tb_env = env->tb_env;
uint64_t tb; uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset);
tb &= 0xFFFFFFFF00000000ULL; tb &= 0xFFFFFFFF00000000ULL;
cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock),
&tb_env->atb_offset, tb | (uint64_t)value); &tb_env->atb_offset, tb | (uint64_t)value);
} }
@ -514,9 +514,9 @@ void cpu_ppc_store_atbu (CPUState *env, uint32_t value)
ppc_tb_t *tb_env = env->tb_env; ppc_tb_t *tb_env = env->tb_env;
uint64_t tb; uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset);
tb &= 0x00000000FFFFFFFFULL; tb &= 0x00000000FFFFFFFFULL;
cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock),
&tb_env->atb_offset, ((uint64_t)value << 32) | tb); &tb_env->atb_offset, ((uint64_t)value << 32) | tb);
} }
@ -527,7 +527,7 @@ static void cpu_ppc_tb_stop (CPUState *env)
/* If the time base is already frozen, do nothing */ /* If the time base is already frozen, do nothing */
if (tb_env->tb_freq != 0) { if (tb_env->tb_freq != 0) {
vmclk = qemu_get_clock(vm_clock); vmclk = qemu_get_clock_ns(vm_clock);
/* Get the time base */ /* Get the time base */
tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset); tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset);
/* Get the alternate time base */ /* Get the alternate time base */
@ -549,7 +549,7 @@ static void cpu_ppc_tb_start (CPUState *env)
/* If the time base is not frozen, do nothing */ /* If the time base is not frozen, do nothing */
if (tb_env->tb_freq == 0) { if (tb_env->tb_freq == 0) {
vmclk = qemu_get_clock(vm_clock); vmclk = qemu_get_clock_ns(vm_clock);
/* Get the time base from tb_offset */ /* Get the time base from tb_offset */
tb = tb_env->tb_offset; tb = tb_env->tb_offset;
/* Get the alternate time base from atb_offset */ /* Get the alternate time base from atb_offset */
@ -569,7 +569,7 @@ static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next)
uint32_t decr; uint32_t decr;
int64_t diff; int64_t diff;
diff = next - qemu_get_clock(vm_clock); diff = next - qemu_get_clock_ns(vm_clock);
if (diff >= 0) if (diff >= 0)
decr = muldiv64(diff, tb_env->decr_freq, get_ticks_per_sec()); decr = muldiv64(diff, tb_env->decr_freq, get_ticks_per_sec());
else else
@ -598,7 +598,7 @@ uint64_t cpu_ppc_load_purr (CPUState *env)
ppc_tb_t *tb_env = env->tb_env; ppc_tb_t *tb_env = env->tb_env;
uint64_t diff; uint64_t diff;
diff = qemu_get_clock(vm_clock) - tb_env->purr_start; diff = qemu_get_clock_ns(vm_clock) - tb_env->purr_start;
return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, get_ticks_per_sec()); return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, get_ticks_per_sec());
} }
@ -631,7 +631,7 @@ static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp,
LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__, LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__,
decr, value); decr, value);
now = qemu_get_clock(vm_clock); now = qemu_get_clock_ns(vm_clock);
next = now + muldiv64(value, get_ticks_per_sec(), tb_env->decr_freq); next = now + muldiv64(value, get_ticks_per_sec(), tb_env->decr_freq);
if (is_excp) if (is_excp)
next += *nextp - now; next += *nextp - now;
@ -692,7 +692,7 @@ void cpu_ppc_store_purr (CPUState *env, uint64_t value)
ppc_tb_t *tb_env = env->tb_env; ppc_tb_t *tb_env = env->tb_env;
tb_env->purr_load = value; tb_env->purr_load = value;
tb_env->purr_start = qemu_get_clock(vm_clock); tb_env->purr_start = qemu_get_clock_ns(vm_clock);
} }
static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
@ -719,11 +719,11 @@ clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq)
tb_env = qemu_mallocz(sizeof(ppc_tb_t)); tb_env = qemu_mallocz(sizeof(ppc_tb_t));
env->tb_env = tb_env; env->tb_env = tb_env;
/* Create new timer */ /* Create new timer */
tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env); tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &cpu_ppc_decr_cb, env);
if (0) { if (0) {
/* XXX: find a suitable condition to enable the hypervisor decrementer /* XXX: find a suitable condition to enable the hypervisor decrementer
*/ */
tb_env->hdecr_timer = qemu_new_timer(vm_clock, &cpu_ppc_hdecr_cb, env); tb_env->hdecr_timer = qemu_new_timer_ns(vm_clock, &cpu_ppc_hdecr_cb, env);
} else { } else {
tb_env->hdecr_timer = NULL; tb_env->hdecr_timer = NULL;
} }
@ -787,7 +787,7 @@ static void cpu_4xx_fit_cb (void *opaque)
env = opaque; env = opaque;
tb_env = env->tb_env; tb_env = env->tb_env;
ppcemb_timer = tb_env->opaque; ppcemb_timer = tb_env->opaque;
now = qemu_get_clock(vm_clock); now = qemu_get_clock_ns(vm_clock);
switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
case 0: case 0:
next = 1 << 9; next = 1 << 9;
@ -833,7 +833,7 @@ static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp)
} else { } else {
LOG_TB("%s: start PIT %016" PRIx64 "\n", LOG_TB("%s: start PIT %016" PRIx64 "\n",
__func__, ppcemb_timer->pit_reload); __func__, ppcemb_timer->pit_reload);
now = qemu_get_clock(vm_clock); now = qemu_get_clock_ns(vm_clock);
next = now + muldiv64(ppcemb_timer->pit_reload, next = now + muldiv64(ppcemb_timer->pit_reload,
get_ticks_per_sec(), tb_env->decr_freq); get_ticks_per_sec(), tb_env->decr_freq);
if (is_excp) if (is_excp)
@ -877,7 +877,7 @@ static void cpu_4xx_wdt_cb (void *opaque)
env = opaque; env = opaque;
tb_env = env->tb_env; tb_env = env->tb_env;
ppcemb_timer = tb_env->opaque; ppcemb_timer = tb_env->opaque;
now = qemu_get_clock(vm_clock); now = qemu_get_clock_ns(vm_clock);
switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
case 0: case 0:
next = 1 << 17; next = 1 << 17;
@ -1002,11 +1002,11 @@ clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq,
LOG_TB("%s freq %" PRIu32 "\n", __func__, freq); LOG_TB("%s freq %" PRIu32 "\n", __func__, freq);
if (ppcemb_timer != NULL) { if (ppcemb_timer != NULL) {
/* We use decr timer for PIT */ /* We use decr timer for PIT */
tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env); tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &cpu_4xx_pit_cb, env);
ppcemb_timer->fit_timer = ppcemb_timer->fit_timer =
qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env); qemu_new_timer_ns(vm_clock, &cpu_4xx_fit_cb, env);
ppcemb_timer->wdt_timer = ppcemb_timer->wdt_timer =
qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env); qemu_new_timer_ns(vm_clock, &cpu_4xx_wdt_cb, env);
ppcemb_timer->decr_excp = decr_excp; ppcemb_timer->decr_excp = decr_excp;
} }

6
hw/ppc405_uc.c
View file

@ -1347,7 +1347,7 @@ static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
switch (addr) { switch (addr) {
case 0x00: case 0x00:
/* Time base counter */ /* Time base counter */
ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset, ret = muldiv64(qemu_get_clock_ns(vm_clock) + gpt->tb_offset,
gpt->tb_freq, get_ticks_per_sec()); gpt->tb_freq, get_ticks_per_sec());
break; break;
case 0x10: case 0x10:
@ -1404,7 +1404,7 @@ static void ppc4xx_gpt_writel (void *opaque,
case 0x00: case 0x00:
/* Time base counter */ /* Time base counter */
gpt->tb_offset = muldiv64(value, get_ticks_per_sec(), gpt->tb_freq) gpt->tb_offset = muldiv64(value, get_ticks_per_sec(), gpt->tb_freq)
- qemu_get_clock(vm_clock); - qemu_get_clock_ns(vm_clock);
ppc4xx_gpt_compute_timer(gpt); ppc4xx_gpt_compute_timer(gpt);
break; break;
case 0x10: case 0x10:
@ -1501,7 +1501,7 @@ static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
for (i = 0; i < 5; i++) { for (i = 0; i < 5; i++) {
gpt->irqs[i] = irqs[i]; gpt->irqs[i] = irqs[i];
} }
gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt); gpt->timer = qemu_new_timer_ns(vm_clock, &ppc4xx_gpt_cb, gpt);
#ifdef DEBUG_GPT #ifdef DEBUG_GPT
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif #endif

2
hw/ppc_prep.c
View file

@ -105,7 +105,7 @@ static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
{ {
#if 0 #if 0
int out; int out;
out = pit_get_out(pit, 2, qemu_get_clock(vm_clock)); out = pit_get_out(pit, 2, qemu_get_clock_ns(vm_clock));
dummy_refresh_clock ^= 1; dummy_refresh_clock ^= 1;
return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) | return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
(dummy_refresh_clock << 4); (dummy_refresh_clock << 4);

14
hw/ptimer.c
View file

@ -68,7 +68,7 @@ uint64_t ptimer_get_count(ptimer_state *s)
uint64_t counter; uint64_t counter;
if (s->enabled) { if (s->enabled) {
now = qemu_get_clock(vm_clock); now = qemu_get_clock_ns(vm_clock);
/* Figure out the current counter value. */ /* Figure out the current counter value. */
if (now - s->next_event > 0 if (now - s->next_event > 0
|| s->period == 0) { || s->period == 0) {
@ -122,7 +122,7 @@ void ptimer_set_count(ptimer_state *s, uint64_t count)
{ {
s->delta = count; s->delta = count;
if (s->enabled) { if (s->enabled) {
s->next_event = qemu_get_clock(vm_clock); s->next_event = qemu_get_clock_ns(vm_clock);
ptimer_reload(s); ptimer_reload(s);
} }
} }
@ -137,7 +137,7 @@ void ptimer_run(ptimer_state *s, int oneshot)
return; return;
} }
s->enabled = oneshot ? 2 : 1; s->enabled = oneshot ? 2 : 1;
s->next_event = qemu_get_clock(vm_clock); s->next_event = qemu_get_clock_ns(vm_clock);
ptimer_reload(s); ptimer_reload(s);
} }
@ -159,7 +159,7 @@ void ptimer_set_period(ptimer_state *s, int64_t period)
s->period = period; s->period = period;
s->period_frac = 0; s->period_frac = 0;
if (s->enabled) { if (s->enabled) {
s->next_event = qemu_get_clock(vm_clock); s->next_event = qemu_get_clock_ns(vm_clock);
ptimer_reload(s); ptimer_reload(s);
} }
} }
@ -170,7 +170,7 @@ void ptimer_set_freq(ptimer_state *s, uint32_t freq)
s->period = 1000000000ll / freq; s->period = 1000000000ll / freq;
s->period_frac = (1000000000ll << 32) / freq; s->period_frac = (1000000000ll << 32) / freq;
if (s->enabled) { if (s->enabled) {
s->next_event = qemu_get_clock(vm_clock); s->next_event = qemu_get_clock_ns(vm_clock);
ptimer_reload(s); ptimer_reload(s);
} }
} }
@ -183,7 +183,7 @@ void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload)
if (reload) if (reload)
s->delta = limit; s->delta = limit;
if (s->enabled && reload) { if (s->enabled && reload) {
s->next_event = qemu_get_clock(vm_clock); s->next_event = qemu_get_clock_ns(vm_clock);
ptimer_reload(s); ptimer_reload(s);
} }
} }
@ -239,6 +239,6 @@ ptimer_state *ptimer_init(QEMUBH *bh)
s = (ptimer_state *)qemu_mallocz(sizeof(ptimer_state)); s = (ptimer_state *)qemu_mallocz(sizeof(ptimer_state));
s->bh = bh; s->bh = bh;
s->timer = qemu_new_timer(vm_clock, ptimer_tick, s); s->timer = qemu_new_timer_ns(vm_clock, ptimer_tick, s);
return s; return s;
} }

28
hw/pxa2xx.c
View file

@ -372,7 +372,7 @@ static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)
return s->pmnc; return s->pmnc;
case CPCCNT: case CPCCNT:
if (s->pmnc & 1) if (s->pmnc & 1)
return qemu_get_clock(vm_clock); return qemu_get_clock_ns(vm_clock);
else else
return 0; return 0;
case CPINTEN: case CPINTEN:
@ -921,7 +921,7 @@ static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s)
static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s) static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s)
{ {
int64_t rt = qemu_get_clock(rt_clock); int64_t rt = qemu_get_clock_ms(rt_clock);
s->last_rcnr += ((rt - s->last_hz) << 15) / s->last_rcnr += ((rt - s->last_hz) << 15) /
(1000 * ((s->rttr & 0xffff) + 1)); (1000 * ((s->rttr & 0xffff) + 1));
s->last_rdcr += ((rt - s->last_hz) << 15) / s->last_rdcr += ((rt - s->last_hz) << 15) /
@ -931,7 +931,7 @@ static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s)
static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s) static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s)
{ {
int64_t rt = qemu_get_clock(rt_clock); int64_t rt = qemu_get_clock_ms(rt_clock);
if (s->rtsr & (1 << 12)) if (s->rtsr & (1 << 12))
s->last_swcr += (rt - s->last_sw) / 10; s->last_swcr += (rt - s->last_sw) / 10;
s->last_sw = rt; s->last_sw = rt;
@ -939,7 +939,7 @@ static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s)
static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s) static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s)
{ {
int64_t rt = qemu_get_clock(rt_clock); int64_t rt = qemu_get_clock_ms(rt_clock);
if (s->rtsr & (1 << 15)) if (s->rtsr & (1 << 15))
s->last_swcr += rt - s->last_pi; s->last_swcr += rt - s->last_pi;
s->last_pi = rt; s->last_pi = rt;
@ -1064,16 +1064,16 @@ static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
case PIAR: case PIAR:
return s->piar; return s->piar;
case RCNR: case RCNR:
return s->last_rcnr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) / return s->last_rcnr + ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /
(1000 * ((s->rttr & 0xffff) + 1)); (1000 * ((s->rttr & 0xffff) + 1));
case RDCR: case RDCR:
return s->last_rdcr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) / return s->last_rdcr + ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /
(1000 * ((s->rttr & 0xffff) + 1)); (1000 * ((s->rttr & 0xffff) + 1));
case RYCR: case RYCR:
return s->last_rycr; return s->last_rycr;
case SWCR: case SWCR:
if (s->rtsr & (1 << 12)) if (s->rtsr & (1 << 12))
return s->last_swcr + (qemu_get_clock(rt_clock) - s->last_sw) / 10; return s->last_swcr + (qemu_get_clock_ms(rt_clock) - s->last_sw) / 10;
else else
return s->last_swcr; return s->last_swcr;
default: default:
@ -1219,14 +1219,14 @@ static int pxa2xx_rtc_init(SysBusDevice *dev)
s->last_swcr = (tm.tm_hour << 19) | s->last_swcr = (tm.tm_hour << 19) |
(tm.tm_min << 13) | (tm.tm_sec << 7); (tm.tm_min << 13) | (tm.tm_sec << 7);
s->last_rtcpicr = 0; s->last_rtcpicr = 0;
s->last_hz = s->last_sw = s->last_pi = qemu_get_clock(rt_clock); s->last_hz = s->last_sw = s->last_pi = qemu_get_clock_ms(rt_clock);
s->rtc_hz = qemu_new_timer(rt_clock, pxa2xx_rtc_hz_tick, s); s->rtc_hz = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_hz_tick, s);
s->rtc_rdal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal1_tick, s); s->rtc_rdal1 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_rdal1_tick, s);
s->rtc_rdal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal2_tick, s); s->rtc_rdal2 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_rdal2_tick, s);
s->rtc_swal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal1_tick, s); s->rtc_swal1 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_swal1_tick, s);
s->rtc_swal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal2_tick, s); s->rtc_swal2 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_swal2_tick, s);
s->rtc_pi = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick, s); s->rtc_pi = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_pi_tick, s);
sysbus_init_irq(dev, &s->rtc_irq); sysbus_init_irq(dev, &s->rtc_irq);

28
hw/pxa2xx_timer.c
View file

@ -171,7 +171,7 @@ static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset)
goto badreg; goto badreg;
return s->tm4[tm].tm.value; return s->tm4[tm].tm.value;
case OSCR: case OSCR:
return s->clock + muldiv64(qemu_get_clock(vm_clock) - return s->clock + muldiv64(qemu_get_clock_ns(vm_clock) -
s->lastload, s->freq, get_ticks_per_sec()); s->lastload, s->freq, get_ticks_per_sec());
case OSCR11: tm ++; case OSCR11: tm ++;
case OSCR10: tm ++; case OSCR10: tm ++;
@ -187,7 +187,7 @@ static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset)
if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) { if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
if (s->tm4[tm - 1].freq) if (s->tm4[tm - 1].freq)
s->snapshot = s->tm4[tm - 1].clock + muldiv64( s->snapshot = s->tm4[tm - 1].clock + muldiv64(
qemu_get_clock(vm_clock) - qemu_get_clock_ns(vm_clock) -
s->tm4[tm - 1].lastload, s->tm4[tm - 1].lastload,
s->tm4[tm - 1].freq, get_ticks_per_sec()); s->tm4[tm - 1].freq, get_ticks_per_sec());
else else
@ -196,7 +196,7 @@ static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset)
if (!s->tm4[tm].freq) if (!s->tm4[tm].freq)
return s->tm4[tm].clock; return s->tm4[tm].clock;
return s->tm4[tm].clock + muldiv64(qemu_get_clock(vm_clock) - return s->tm4[tm].clock + muldiv64(qemu_get_clock_ns(vm_clock) -
s->tm4[tm].lastload, s->tm4[tm].freq, get_ticks_per_sec()); s->tm4[tm].lastload, s->tm4[tm].freq, get_ticks_per_sec());
case OIER: case OIER:
return s->irq_enabled; return s->irq_enabled;
@ -237,7 +237,7 @@ static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
case OSMR1: tm ++; case OSMR1: tm ++;
case OSMR0: case OSMR0:
s->timer[tm].value = value; s->timer[tm].value = value;
pxa2xx_timer_update(s, qemu_get_clock(vm_clock)); pxa2xx_timer_update(s, qemu_get_clock_ns(vm_clock));
break; break;
case OSMR11: tm ++; case OSMR11: tm ++;
case OSMR10: tm ++; case OSMR10: tm ++;
@ -250,11 +250,11 @@ static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
if (!pxa2xx_timer_has_tm4(s)) if (!pxa2xx_timer_has_tm4(s))
goto badreg; goto badreg;
s->tm4[tm].tm.value = value; s->tm4[tm].tm.value = value;
pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm); pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm);
break; break;
case OSCR: case OSCR:
s->oldclock = s->clock; s->oldclock = s->clock;
s->lastload = qemu_get_clock(vm_clock); s->lastload = qemu_get_clock_ns(vm_clock);
s->clock = value; s->clock = value;
pxa2xx_timer_update(s, s->lastload); pxa2xx_timer_update(s, s->lastload);
break; break;
@ -269,7 +269,7 @@ static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
if (!pxa2xx_timer_has_tm4(s)) if (!pxa2xx_timer_has_tm4(s))
goto badreg; goto badreg;
s->tm4[tm].oldclock = s->tm4[tm].clock; s->tm4[tm].oldclock = s->tm4[tm].clock;
s->tm4[tm].lastload = qemu_get_clock(vm_clock); s->tm4[tm].lastload = qemu_get_clock_ns(vm_clock);
s->tm4[tm].clock = value; s->tm4[tm].clock = value;
pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm); pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
break; break;
@ -300,7 +300,7 @@ static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7]; s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
else { else {
s->tm4[tm].freq = 0; s->tm4[tm].freq = 0;
pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm); pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm);
} }
break; break;
case OMCR11: tm ++; case OMCR11: tm ++;
@ -316,7 +316,7 @@ static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)]; pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)];
else { else {
s->tm4[tm].freq = 0; s->tm4[tm].freq = 0;
pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm); pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm);
} }
break; break;
default: default:
@ -363,7 +363,7 @@ static void pxa2xx_timer_tick4(void *opaque)
if (t->control & (1 << 3)) if (t->control & (1 << 3))
t->clock = 0; t->clock = 0;
if (t->control & (1 << 6)) if (t->control & (1 << 6))
pxa2xx_timer_update4(i, qemu_get_clock(vm_clock), t->tm.num - 4); pxa2xx_timer_update4(i, qemu_get_clock_ns(vm_clock), t->tm.num - 4);
if (i->events & 0xff0) if (i->events & 0xff0)
qemu_irq_raise(i->irq4); qemu_irq_raise(i->irq4);
} }
@ -374,7 +374,7 @@ static int pxa25x_timer_post_load(void *opaque, int version_id)
int64_t now; int64_t now;
int i; int i;
now = qemu_get_clock(vm_clock); now = qemu_get_clock_ns(vm_clock);
pxa2xx_timer_update(s, now); pxa2xx_timer_update(s, now);
if (pxa2xx_timer_has_tm4(s)) if (pxa2xx_timer_has_tm4(s))
@ -394,7 +394,7 @@ static int pxa2xx_timer_init(SysBusDevice *dev)
s->irq_enabled = 0; s->irq_enabled = 0;
s->oldclock = 0; s->oldclock = 0;
s->clock = 0; s->clock = 0;
s->lastload = qemu_get_clock(vm_clock); s->lastload = qemu_get_clock_ns(vm_clock);
s->reset3 = 0; s->reset3 = 0;
for (i = 0; i < 4; i ++) { for (i = 0; i < 4; i ++) {
@ -402,7 +402,7 @@ static int pxa2xx_timer_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->timer[i].irq); sysbus_init_irq(dev, &s->timer[i].irq);
s->timer[i].info = s; s->timer[i].info = s;
s->timer[i].num = i; s->timer[i].num = i;
s->timer[i].qtimer = qemu_new_timer(vm_clock, s->timer[i].qtimer = qemu_new_timer_ns(vm_clock,
pxa2xx_timer_tick, &s->timer[i]); pxa2xx_timer_tick, &s->timer[i]);
} }
if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) { if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) {
@ -414,7 +414,7 @@ static int pxa2xx_timer_init(SysBusDevice *dev)
s->tm4[i].tm.num = i + 4; s->tm4[i].tm.num = i + 4;
s->tm4[i].freq = 0; s->tm4[i].freq = 0;
s->tm4[i].control = 0x0; s->tm4[i].control = 0x0;
s->tm4[i].tm.qtimer = qemu_new_timer(vm_clock, s->tm4[i].tm.qtimer = qemu_new_timer_ns(vm_clock,
pxa2xx_timer_tick4, &s->tm4[i]); pxa2xx_timer_tick4, &s->tm4[i]);
} }
} }

4
hw/rc4030.c
View file

@ -104,7 +104,7 @@ static void set_next_tick(rc4030State *s)
tm_hz = 1000 / (s->itr + 1); tm_hz = 1000 / (s->itr + 1);
qemu_mod_timer(s->periodic_timer, qemu_get_clock(vm_clock) + qemu_mod_timer(s->periodic_timer, qemu_get_clock_ns(vm_clock) +
get_ticks_per_sec() / tm_hz); get_ticks_per_sec() / tm_hz);
} }
@ -811,7 +811,7 @@ void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
*irqs = qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16); *irqs = qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16);
*dmas = rc4030_allocate_dmas(s, 4); *dmas = rc4030_allocate_dmas(s, 4);
s->periodic_timer = qemu_new_timer(vm_clock, rc4030_periodic_timer, s); s->periodic_timer = qemu_new_timer_ns(vm_clock, rc4030_periodic_timer, s);
s->timer_irq = timer; s->timer_irq = timer;
s->jazz_bus_irq = jazz_bus; s->jazz_bus_irq = jazz_bus;

22
hw/rtl8139.c
View file

@ -2517,7 +2517,7 @@ static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
s->IntrMask = val; s->IntrMask = val;
rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock)); rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
rtl8139_update_irq(s); rtl8139_update_irq(s);
} }
@ -2558,7 +2558,7 @@ static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
* and probably emulated is slower is better to assume this resetting was * and probably emulated is slower is better to assume this resetting was
* done before testing on previous rtl8139_update_irq lead to IRQ loosing * done before testing on previous rtl8139_update_irq lead to IRQ loosing
*/ */
rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock)); rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
rtl8139_update_irq(s); rtl8139_update_irq(s);
#endif #endif
@ -2566,7 +2566,7 @@ static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
static uint32_t rtl8139_IntrStatus_read(RTL8139State *s) static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
{ {
rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock)); rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
uint32_t ret = s->IntrStatus; uint32_t ret = s->IntrStatus;
@ -2831,7 +2831,7 @@ static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
case Timer: case Timer:
DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n")); DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n"));
s->TCTR_base = qemu_get_clock(vm_clock); s->TCTR_base = qemu_get_clock_ns(vm_clock);
rtl8139_set_next_tctr_time(s, s->TCTR_base); rtl8139_set_next_tctr_time(s, s->TCTR_base);
break; break;
@ -2839,7 +2839,7 @@ static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val)); DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val));
if (s->TimerInt != val) { if (s->TimerInt != val) {
s->TimerInt = val; s->TimerInt = val;
rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock)); rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
} }
break; break;
@ -3050,7 +3050,7 @@ static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
break; break;
case Timer: case Timer:
ret = muldiv64(qemu_get_clock(vm_clock) - s->TCTR_base, ret = muldiv64(qemu_get_clock_ns(vm_clock) - s->TCTR_base,
PCI_FREQUENCY, get_ticks_per_sec()); PCI_FREQUENCY, get_ticks_per_sec());
DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret)); DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret));
break; break;
@ -3144,7 +3144,7 @@ static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
static int rtl8139_post_load(void *opaque, int version_id) static int rtl8139_post_load(void *opaque, int version_id)
{ {
RTL8139State* s = opaque; RTL8139State* s = opaque;
rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock)); rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
if (version_id < 4) { if (version_id < 4) {
s->cplus_enabled = s->CpCmd != 0; s->cplus_enabled = s->CpCmd != 0;
} }
@ -3170,7 +3170,7 @@ static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
static void rtl8139_pre_save(void *opaque) static void rtl8139_pre_save(void *opaque)
{ {
RTL8139State* s = opaque; RTL8139State* s = opaque;
int64_t current_time = qemu_get_clock(vm_clock); int64_t current_time = qemu_get_clock_ns(vm_clock);
/* set IntrStatus correctly */ /* set IntrStatus correctly */
rtl8139_set_next_tctr_time(s, current_time); rtl8139_set_next_tctr_time(s, current_time);
@ -3319,7 +3319,7 @@ static void rtl8139_timer(void *opaque)
s->IntrStatus |= PCSTimeout; s->IntrStatus |= PCSTimeout;
rtl8139_update_irq(s); rtl8139_update_irq(s);
rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock)); rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
} }
static void rtl8139_cleanup(VLANClientState *nc) static void rtl8139_cleanup(VLANClientState *nc)
@ -3400,8 +3400,8 @@ static int pci_rtl8139_init(PCIDevice *dev)
s->cplus_txbuffer_offset = 0; s->cplus_txbuffer_offset = 0;
s->TimerExpire = 0; s->TimerExpire = 0;
s->timer = qemu_new_timer(vm_clock, rtl8139_timer, s); s->timer = qemu_new_timer_ns(vm_clock, rtl8139_timer, s);
rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock)); rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0"); add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0");

4
hw/sb16.c
View file

@ -766,7 +766,7 @@ static void complete (SB16State *s)
if (s->aux_ts) { if (s->aux_ts) {
qemu_mod_timer ( qemu_mod_timer (
s->aux_ts, s->aux_ts,
qemu_get_clock (vm_clock) + ticks qemu_get_clock_ns (vm_clock) + ticks
); );
} }
} }
@ -1361,7 +1361,7 @@ static int sb16_initfn (ISADevice *dev)
s->csp_regs[9] = 0xf8; s->csp_regs[9] = 0xf8;
reset_mixer (s); reset_mixer (s);
s->aux_ts = qemu_new_timer (vm_clock, aux_timer, s); s->aux_ts = qemu_new_timer_ns (vm_clock, aux_timer, s);
if (!s->aux_ts) { if (!s->aux_ts) {
dolog ("warning: Could not create auxiliary timer\n"); dolog ("warning: Could not create auxiliary timer\n");
} }

20
hw/serial.c
View file

@ -312,13 +312,13 @@ static void serial_update_msl(SerialState *s)
We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */ We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
if (s->poll_msl) if (s->poll_msl)
qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + get_ticks_per_sec() / 100); qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 100);
} }
static void serial_xmit(void *opaque) static void serial_xmit(void *opaque)
{ {
SerialState *s = opaque; SerialState *s = opaque;
uint64_t new_xmit_ts = qemu_get_clock(vm_clock); uint64_t new_xmit_ts = qemu_get_clock_ns(vm_clock);
if (s->tsr_retry <= 0) { if (s->tsr_retry <= 0) {
if (s->fcr & UART_FCR_FE) { if (s->fcr & UART_FCR_FE) {
@ -350,7 +350,7 @@ static void serial_xmit(void *opaque)
s->tsr_retry = 0; s->tsr_retry = 0;
} }
s->last_xmit_ts = qemu_get_clock(vm_clock); s->last_xmit_ts = qemu_get_clock_ns(vm_clock);
if (!(s->lsr & UART_LSR_THRE)) if (!(s->lsr & UART_LSR_THRE))
qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time); qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time);
@ -494,7 +494,7 @@ static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags); qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
/* Update the modem status after a one-character-send wait-time, since there may be a response /* Update the modem status after a one-character-send wait-time, since there may be a response
from the device/computer at the other end of the serial line */ from the device/computer at the other end of the serial line */
qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + s->char_transmit_time); qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + s->char_transmit_time);
} }
} }
break; break;
@ -525,7 +525,7 @@ static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
if (s->recv_fifo.count == 0) if (s->recv_fifo.count == 0)
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
else else
qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4); qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
s->timeout_ipending = 0; s->timeout_ipending = 0;
} else { } else {
ret = s->rbr; ret = s->rbr;
@ -641,7 +641,7 @@ static void serial_receive1(void *opaque, const uint8_t *buf, int size)
} }
s->lsr |= UART_LSR_DR; s->lsr |= UART_LSR_DR;
/* call the timeout receive callback in 4 char transmit time */ /* call the timeout receive callback in 4 char transmit time */
qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4); qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
} else { } else {
if (s->lsr & UART_LSR_DR) if (s->lsr & UART_LSR_DR)
s->lsr |= UART_LSR_OE; s->lsr |= UART_LSR_OE;
@ -720,7 +720,7 @@ static void serial_reset(void *opaque)
fifo_clear(s,RECV_FIFO); fifo_clear(s,RECV_FIFO);
fifo_clear(s,XMIT_FIFO); fifo_clear(s,XMIT_FIFO);
s->last_xmit_ts = qemu_get_clock(vm_clock); s->last_xmit_ts = qemu_get_clock_ns(vm_clock);
s->thr_ipending = 0; s->thr_ipending = 0;
s->last_break_enable = 0; s->last_break_enable = 0;
@ -734,10 +734,10 @@ static void serial_init_core(SerialState *s)
exit(1); exit(1);
} }
s->modem_status_poll = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_update_msl, s); s->modem_status_poll = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_update_msl, s);
s->fifo_timeout_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s); s->fifo_timeout_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s);
s->transmit_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_xmit, s); s->transmit_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_xmit, s);
qemu_register_reset(serial_reset, s); qemu_register_reset(serial_reset, s);

4
hw/soc_dma.c
View file

@ -84,7 +84,7 @@ struct dma_s {
static void soc_dma_ch_schedule(struct soc_dma_ch_s *ch, int delay_bytes) static void soc_dma_ch_schedule(struct soc_dma_ch_s *ch, int delay_bytes)
{ {
int64_t now = qemu_get_clock(vm_clock); int64_t now = qemu_get_clock_ns(vm_clock);
struct dma_s *dma = (struct dma_s *) ch->dma; struct dma_s *dma = (struct dma_s *) ch->dma;
qemu_mod_timer(ch->timer, now + delay_bytes / dma->channel_freq); qemu_mod_timer(ch->timer, now + delay_bytes / dma->channel_freq);
@ -246,7 +246,7 @@ struct soc_dma_s *soc_dma_init(int n)
for (i = 0; i < n; i ++) { for (i = 0; i < n; i ++) {
s->ch[i].dma = &s->soc; s->ch[i].dma = &s->soc;
s->ch[i].num = i; s->ch[i].num = i;
s->ch[i].timer = qemu_new_timer(vm_clock, soc_dma_ch_run, &s->ch[i]); s->ch[i].timer = qemu_new_timer_ns(vm_clock, soc_dma_ch_run, &s->ch[i]);
} }
soc_dma_reset(&s->soc); soc_dma_reset(&s->soc);

6
hw/spitz.c
View file

@ -393,7 +393,7 @@ static void spitz_keyboard_tick(void *opaque)
s->fifopos = 0; s->fifopos = 0;
} }
qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock) + qemu_mod_timer(s->kbdtimer, qemu_get_clock_ns(vm_clock) +
get_ticks_per_sec() / 32); get_ticks_per_sec() / 32);
} }
@ -485,7 +485,7 @@ static void spitz_keyboard_register(PXA2xxState *cpu)
qdev_connect_gpio_out(cpu->gpio, spitz_gpio_key_strobe[i], qdev_connect_gpio_out(cpu->gpio, spitz_gpio_key_strobe[i],
qdev_get_gpio_in(dev, i)); qdev_get_gpio_in(dev, i));
qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock)); qemu_mod_timer(s->kbdtimer, qemu_get_clock_ns(vm_clock));
qemu_add_kbd_event_handler(spitz_keyboard_handler, s); qemu_add_kbd_event_handler(spitz_keyboard_handler, s);
} }
@ -506,7 +506,7 @@ static int spitz_keyboard_init(SysBusDevice *dev)
spitz_keyboard_pre_map(s); spitz_keyboard_pre_map(s);
s->kbdtimer = qemu_new_timer(vm_clock, spitz_keyboard_tick, s); s->kbdtimer = qemu_new_timer_ns(vm_clock, spitz_keyboard_tick, s);
qdev_init_gpio_in(&dev->qdev, spitz_keyboard_strobe, SPITZ_KEY_STROBE_NUM); qdev_init_gpio_in(&dev->qdev, spitz_keyboard_strobe, SPITZ_KEY_STROBE_NUM);
qdev_init_gpio_out(&dev->qdev, s->sense, SPITZ_KEY_SENSE_NUM); qdev_init_gpio_out(&dev->qdev, s->sense, SPITZ_KEY_SENSE_NUM);

6
hw/stellaris.c
View file

@ -79,7 +79,7 @@ static void gptm_reload(gptm_state *s, int n, int reset)
{ {
int64_t tick; int64_t tick;
if (reset) if (reset)
tick = qemu_get_clock(vm_clock); tick = qemu_get_clock_ns(vm_clock);
else else
tick = s->tick[n]; tick = s->tick[n];
@ -353,8 +353,8 @@ static int stellaris_gptm_init(SysBusDevice *dev)
sysbus_init_mmio(dev, 0x1000, iomemtype); sysbus_init_mmio(dev, 0x1000, iomemtype);
s->opaque[0] = s->opaque[1] = s; s->opaque[0] = s->opaque[1] = s;
s->timer[0] = qemu_new_timer(vm_clock, gptm_tick, &s->opaque[0]); s->timer[0] = qemu_new_timer_ns(vm_clock, gptm_tick, &s->opaque[0]);
s->timer[1] = qemu_new_timer(vm_clock, gptm_tick, &s->opaque[1]); s->timer[1] = qemu_new_timer_ns(vm_clock, gptm_tick, &s->opaque[1]);
register_savevm(&dev->qdev, "stellaris_gptm", -1, 1, register_savevm(&dev->qdev, "stellaris_gptm", -1, 1,
gptm_save, gptm_load, s); gptm_save, gptm_load, s);
return 0; return 0;

12
hw/sun4u.c
View file

@ -352,9 +352,9 @@ static CPUTimer* cpu_timer_create(const char* name, CPUState *env,
timer->disabled_mask = disabled_mask; timer->disabled_mask = disabled_mask;
timer->disabled = 1; timer->disabled = 1;
timer->clock_offset = qemu_get_clock(vm_clock); timer->clock_offset = qemu_get_clock_ns(vm_clock);
timer->qtimer = qemu_new_timer(vm_clock, cb, env); timer->qtimer = qemu_new_timer_ns(vm_clock, cb, env);
return timer; return timer;
} }
@ -362,7 +362,7 @@ static CPUTimer* cpu_timer_create(const char* name, CPUState *env,
static void cpu_timer_reset(CPUTimer *timer) static void cpu_timer_reset(CPUTimer *timer)
{ {
timer->disabled = 1; timer->disabled = 1;
timer->clock_offset = qemu_get_clock(vm_clock); timer->clock_offset = qemu_get_clock_ns(vm_clock);
qemu_del_timer(timer->qtimer); qemu_del_timer(timer->qtimer);
} }
@ -457,7 +457,7 @@ void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
uint64_t real_count = count & ~timer->disabled_mask; uint64_t real_count = count & ~timer->disabled_mask;
uint64_t disabled_bit = count & timer->disabled_mask; uint64_t disabled_bit = count & timer->disabled_mask;
int64_t vm_clock_offset = qemu_get_clock(vm_clock) - int64_t vm_clock_offset = qemu_get_clock_ns(vm_clock) -
cpu_to_timer_ticks(real_count, timer->frequency); cpu_to_timer_ticks(real_count, timer->frequency);
TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n", TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n",
@ -471,7 +471,7 @@ void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
uint64_t cpu_tick_get_count(CPUTimer *timer) uint64_t cpu_tick_get_count(CPUTimer *timer)
{ {
uint64_t real_count = timer_to_cpu_ticks( uint64_t real_count = timer_to_cpu_ticks(
qemu_get_clock(vm_clock) - timer->clock_offset, qemu_get_clock_ns(vm_clock) - timer->clock_offset,
timer->frequency); timer->frequency);
TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n", TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n",
@ -486,7 +486,7 @@ uint64_t cpu_tick_get_count(CPUTimer *timer)
void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit) void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
{ {
int64_t now = qemu_get_clock(vm_clock); int64_t now = qemu_get_clock_ns(vm_clock);
uint64_t real_limit = limit & ~timer->disabled_mask; uint64_t real_limit = limit & ~timer->disabled_mask;
timer->disabled = (limit & timer->disabled_mask) ? 1 : 0; timer->disabled = (limit & timer->disabled_mask) ? 1 : 0;

2
hw/syborg_rtc.c
View file

@ -66,7 +66,7 @@ static void syborg_rtc_write(void *opaque, target_phys_addr_t offset, uint32_t v
offset &= 0xfff; offset &= 0xfff;
switch (offset >> 2) { switch (offset >> 2) {
case RTC_LATCH: case RTC_LATCH:
now = qemu_get_clock(vm_clock); now = qemu_get_clock_ns(vm_clock);
if (value >= 4) { if (value >= 4) {
s->offset = s->data - now; s->offset = s->data - now;
} else { } else {

4
hw/tsc2005.c
View file

@ -290,7 +290,7 @@ static void tsc2005_pin_update(TSC2005State *s)
s->precision = s->nextprecision; s->precision = s->nextprecision;
s->function = s->nextfunction; s->function = s->nextfunction;
s->pdst = !s->pnd0; /* Synchronised on internal clock */ s->pdst = !s->pnd0; /* Synchronised on internal clock */
expires = qemu_get_clock(vm_clock) + (get_ticks_per_sec() >> 7); expires = qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() >> 7);
qemu_mod_timer(s->timer, expires); qemu_mod_timer(s->timer, expires);
} }
@ -529,7 +529,7 @@ void *tsc2005_init(qemu_irq pintdav)
s->y = 240; s->y = 240;
s->pressure = 0; s->pressure = 0;
s->precision = s->nextprecision = 0; s->precision = s->nextprecision = 0;
s->timer = qemu_new_timer(vm_clock, tsc2005_timer_tick, s); s->timer = qemu_new_timer_ns(vm_clock, tsc2005_timer_tick, s);
s->pint = pintdav; s->pint = pintdav;
s->model = 0x2005; s->model = 0x2005;

20
hw/tsc210x.c
View file

@ -503,9 +503,9 @@ static uint16_t tsc2102_audio_register_read(TSC210xState *s, int reg)
l_ch = 1; l_ch = 1;
r_ch = 1; r_ch = 1;
if (s->softstep && !(s->dac_power & (1 << 10))) { if (s->softstep && !(s->dac_power & (1 << 10))) {
l_ch = (qemu_get_clock(vm_clock) > l_ch = (qemu_get_clock_ns(vm_clock) >
s->volume_change + TSC_SOFTSTEP_DELAY); s->volume_change + TSC_SOFTSTEP_DELAY);
r_ch = (qemu_get_clock(vm_clock) > r_ch = (qemu_get_clock_ns(vm_clock) >
s->volume_change + TSC_SOFTSTEP_DELAY); s->volume_change + TSC_SOFTSTEP_DELAY);
} }
@ -514,7 +514,7 @@ static uint16_t tsc2102_audio_register_read(TSC210xState *s, int reg)
case 0x05: /* Stereo DAC Power Control */ case 0x05: /* Stereo DAC Power Control */
return 0x2aa0 | s->dac_power | return 0x2aa0 | s->dac_power |
(((s->dac_power & (1 << 10)) && (((s->dac_power & (1 << 10)) &&
(qemu_get_clock(vm_clock) > (qemu_get_clock_ns(vm_clock) >
s->powerdown + TSC_POWEROFF_DELAY)) << 6); s->powerdown + TSC_POWEROFF_DELAY)) << 6);
case 0x06: /* Audio Control 3 */ case 0x06: /* Audio Control 3 */
@ -695,7 +695,7 @@ static void tsc2102_audio_register_write(
case 0x02: /* DAC Volume Control */ case 0x02: /* DAC Volume Control */
s->volume = value; s->volume = value;
s->volume_change = qemu_get_clock(vm_clock); s->volume_change = qemu_get_clock_ns(vm_clock);
return; return;
case 0x03: case 0x03:
@ -717,7 +717,7 @@ static void tsc2102_audio_register_write(
case 0x05: /* Stereo DAC Power Control */ case 0x05: /* Stereo DAC Power Control */
if ((value & ~s->dac_power) & (1 << 10)) if ((value & ~s->dac_power) & (1 << 10))
s->powerdown = qemu_get_clock(vm_clock); s->powerdown = qemu_get_clock_ns(vm_clock);
s->dac_power = value & 0x9543; s->dac_power = value & 0x9543;
#ifdef TSC_VERBOSE #ifdef TSC_VERBOSE
@ -864,7 +864,7 @@ static void tsc210x_pin_update(TSC210xState *s)
s->busy = 1; s->busy = 1;
s->precision = s->nextprecision; s->precision = s->nextprecision;
s->function = s->nextfunction; s->function = s->nextfunction;
expires = qemu_get_clock(vm_clock) + (get_ticks_per_sec() >> 10); expires = qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() >> 10);
qemu_mod_timer(s->timer, expires); qemu_mod_timer(s->timer, expires);
} }
@ -1005,7 +1005,7 @@ static void tsc210x_i2s_set_rate(TSC210xState *s, int in, int out)
static void tsc210x_save(QEMUFile *f, void *opaque) static void tsc210x_save(QEMUFile *f, void *opaque)
{ {
TSC210xState *s = (TSC210xState *) opaque; TSC210xState *s = (TSC210xState *) opaque;
int64_t now = qemu_get_clock(vm_clock); int64_t now = qemu_get_clock_ns(vm_clock);
int i; int i;
qemu_put_be16(f, s->x); qemu_put_be16(f, s->x);
@ -1051,7 +1051,7 @@ static void tsc210x_save(QEMUFile *f, void *opaque)
static int tsc210x_load(QEMUFile *f, void *opaque, int version_id) static int tsc210x_load(QEMUFile *f, void *opaque, int version_id)
{ {
TSC210xState *s = (TSC210xState *) opaque; TSC210xState *s = (TSC210xState *) opaque;
int64_t now = qemu_get_clock(vm_clock); int64_t now = qemu_get_clock_ns(vm_clock);
int i; int i;
s->x = qemu_get_be16(f); s->x = qemu_get_be16(f);
@ -1111,7 +1111,7 @@ uWireSlave *tsc2102_init(qemu_irq pint)
s->y = 160; s->y = 160;
s->pressure = 0; s->pressure = 0;
s->precision = s->nextprecision = 0; s->precision = s->nextprecision = 0;
s->timer = qemu_new_timer(vm_clock, tsc210x_timer_tick, s); s->timer = qemu_new_timer_ns(vm_clock, tsc210x_timer_tick, s);
s->pint = pint; s->pint = pint;
s->model = 0x2102; s->model = 0x2102;
s->name = "tsc2102"; s->name = "tsc2102";
@ -1160,7 +1160,7 @@ uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, qemu_irq dav)
s->y = 240; s->y = 240;
s->pressure = 0; s->pressure = 0;
s->precision = s->nextprecision = 0; s->precision = s->nextprecision = 0;
s->timer = qemu_new_timer(vm_clock, tsc210x_timer_tick, s); s->timer = qemu_new_timer_ns(vm_clock, tsc210x_timer_tick, s);
s->pint = penirq; s->pint = penirq;
s->kbint = kbirq; s->kbint = kbirq;
s->davint = dav; s->davint = dav;

8
hw/tusb6010.c
View file

@ -520,7 +520,7 @@ static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
case TUSB_DEV_OTG_TIMER: case TUSB_DEV_OTG_TIMER:
s->otg_timer_val = value; s->otg_timer_val = value;
if (value & TUSB_DEV_OTG_TIMER_ENABLE) if (value & TUSB_DEV_OTG_TIMER_ENABLE)
qemu_mod_timer(s->otg_timer, qemu_get_clock(vm_clock) + qemu_mod_timer(s->otg_timer, qemu_get_clock_ns(vm_clock) +
muldiv64(TUSB_DEV_OTG_TIMER_VAL(value), muldiv64(TUSB_DEV_OTG_TIMER_VAL(value),
get_ticks_per_sec(), TUSB_DEVCLOCK)); get_ticks_per_sec(), TUSB_DEVCLOCK));
else else
@ -742,8 +742,8 @@ TUSBState *tusb6010_init(qemu_irq intr)
s->iomemtype[1] = cpu_register_io_memory(tusb_async_readfn, s->iomemtype[1] = cpu_register_io_memory(tusb_async_readfn,
tusb_async_writefn, s, DEVICE_NATIVE_ENDIAN); tusb_async_writefn, s, DEVICE_NATIVE_ENDIAN);
s->irq = intr; s->irq = intr;
s->otg_timer = qemu_new_timer(vm_clock, tusb_otg_tick, s); s->otg_timer = qemu_new_timer_ns(vm_clock, tusb_otg_tick, s);
s->pwr_timer = qemu_new_timer(vm_clock, tusb_power_tick, s); s->pwr_timer = qemu_new_timer_ns(vm_clock, tusb_power_tick, s);
s->musb = musb_init(qemu_allocate_irqs(tusb_musb_core_intr, s, s->musb = musb_init(qemu_allocate_irqs(tusb_musb_core_intr, s,
__musb_irq_max)); __musb_irq_max));
@ -761,6 +761,6 @@ void tusb6010_power(TUSBState *s, int on)
s->intr_ok = 0; s->intr_ok = 0;
tusb_intr_update(s); tusb_intr_update(s);
qemu_mod_timer(s->pwr_timer, qemu_mod_timer(s->pwr_timer,
qemu_get_clock(vm_clock) + get_ticks_per_sec() / 2); qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 2);
} }
} }

8
hw/twl92230.c
View file

@ -74,14 +74,14 @@ static inline void menelaus_update(MenelausState *s)
static inline void menelaus_rtc_start(MenelausState *s) static inline void menelaus_rtc_start(MenelausState *s)
{ {
s->rtc.next += qemu_get_clock(rt_clock); s->rtc.next += qemu_get_clock_ms(rt_clock);
qemu_mod_timer(s->rtc.hz_tm, s->rtc.next); qemu_mod_timer(s->rtc.hz_tm, s->rtc.next);
} }
static inline void menelaus_rtc_stop(MenelausState *s) static inline void menelaus_rtc_stop(MenelausState *s)
{ {
qemu_del_timer(s->rtc.hz_tm); qemu_del_timer(s->rtc.hz_tm);
s->rtc.next -= qemu_get_clock(rt_clock); s->rtc.next -= qemu_get_clock_ms(rt_clock);
if (s->rtc.next < 1) if (s->rtc.next < 1)
s->rtc.next = 1; s->rtc.next = 1;
} }
@ -786,7 +786,7 @@ static void menelaus_pre_save(void *opaque)
{ {
MenelausState *s = opaque; MenelausState *s = opaque;
/* Should be <= 1000 */ /* Should be <= 1000 */
s->rtc_next_vmstate = s->rtc.next - qemu_get_clock(rt_clock); s->rtc_next_vmstate = s->rtc.next - qemu_get_clock_ms(rt_clock);
} }
static int menelaus_post_load(void *opaque, int version_id) static int menelaus_post_load(void *opaque, int version_id)
@ -847,7 +847,7 @@ static int twl92230_init(i2c_slave *i2c)
{ {
MenelausState *s = FROM_I2C_SLAVE(MenelausState, i2c); MenelausState *s = FROM_I2C_SLAVE(MenelausState, i2c);
s->rtc.hz_tm = qemu_new_timer(rt_clock, menelaus_rtc_hz, s); s->rtc.hz_tm = qemu_new_timer_ms(rt_clock, menelaus_rtc_hz, s);
/* Three output pins plus one interrupt pin. */ /* Three output pins plus one interrupt pin. */
qdev_init_gpio_out(&i2c->qdev, s->out, 4); qdev_init_gpio_out(&i2c->qdev, s->out, 4);
qdev_init_gpio_in(&i2c->qdev, menelaus_gpio_set, 3); qdev_init_gpio_in(&i2c->qdev, menelaus_gpio_set, 3);

6
hw/usb-hid.c
View file

@ -796,7 +796,7 @@ static int usb_hid_handle_control(USBDevice *dev, int request, int value,
break; break;
case SET_IDLE: case SET_IDLE:
s->idle = (uint8_t) (value >> 8); s->idle = (uint8_t) (value >> 8);
usb_hid_set_next_idle(s, qemu_get_clock(vm_clock)); usb_hid_set_next_idle(s, qemu_get_clock_ns(vm_clock));
ret = 0; ret = 0;
break; break;
default: default:
@ -815,7 +815,7 @@ static int usb_hid_handle_data(USBDevice *dev, USBPacket *p)
switch(p->pid) { switch(p->pid) {
case USB_TOKEN_IN: case USB_TOKEN_IN:
if (p->devep == 1) { if (p->devep == 1) {
int64_t curtime = qemu_get_clock(vm_clock); int64_t curtime = qemu_get_clock_ns(vm_clock);
if (!s->changed && (!s->idle || s->next_idle_clock - curtime > 0)) if (!s->changed && (!s->idle || s->next_idle_clock - curtime > 0))
return USB_RET_NAK; return USB_RET_NAK;
usb_hid_set_next_idle(s, curtime); usb_hid_set_next_idle(s, curtime);
@ -900,7 +900,7 @@ static int usb_hid_post_load(void *opaque, int version_id)
USBHIDState *s = opaque; USBHIDState *s = opaque;
if (s->idle) { if (s->idle) {
usb_hid_set_next_idle(s, qemu_get_clock(vm_clock)); usb_hid_set_next_idle(s, qemu_get_clock_ns(vm_clock));
} }
return 0; return 0;
} }

4
hw/usb-musb.c
View file

@ -513,9 +513,9 @@ static inline void musb_schedule_cb(USBPacket *packey, void *opaque, int dir)
return musb_cb_tick(opaque); return musb_cb_tick(opaque);
if (!ep->intv_timer[dir]) if (!ep->intv_timer[dir])
ep->intv_timer[dir] = qemu_new_timer(vm_clock, musb_cb_tick, opaque); ep->intv_timer[dir] = qemu_new_timer_ns(vm_clock, musb_cb_tick, opaque);
qemu_mod_timer(ep->intv_timer[dir], qemu_get_clock(vm_clock) + qemu_mod_timer(ep->intv_timer[dir], qemu_get_clock_ns(vm_clock) +
muldiv64(timeout, get_ticks_per_sec(), 8000)); muldiv64(timeout, get_ticks_per_sec(), 8000));
} }

8
hw/usb-ohci.c
View file

@ -1101,7 +1101,7 @@ static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion)
/* Generate a SOF event, and set a timer for EOF */ /* Generate a SOF event, and set a timer for EOF */
static void ohci_sof(OHCIState *ohci) static void ohci_sof(OHCIState *ohci)
{ {
ohci->sof_time = qemu_get_clock(vm_clock); ohci->sof_time = qemu_get_clock_ns(vm_clock);
qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time); qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time);
ohci_set_interrupt(ohci, OHCI_INTR_SF); ohci_set_interrupt(ohci, OHCI_INTR_SF);
} }
@ -1186,12 +1186,12 @@ static void ohci_frame_boundary(void *opaque)
*/ */
static int ohci_bus_start(OHCIState *ohci) static int ohci_bus_start(OHCIState *ohci)
{ {
ohci->eof_timer = qemu_new_timer(vm_clock, ohci->eof_timer = qemu_new_timer_ns(vm_clock,
ohci_frame_boundary, ohci_frame_boundary,
ohci); ohci);
if (ohci->eof_timer == NULL) { if (ohci->eof_timer == NULL) {
fprintf(stderr, "usb-ohci: %s: qemu_new_timer failed\n", ohci->name); fprintf(stderr, "usb-ohci: %s: qemu_new_timer_ns failed\n", ohci->name);
/* TODO: Signal unrecoverable error */ /* TODO: Signal unrecoverable error */
return 0; return 0;
} }
@ -1311,7 +1311,7 @@ static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
/* Being in USB operational state guarnatees sof_time was /* Being in USB operational state guarnatees sof_time was
* set already. * set already.
*/ */
tks = qemu_get_clock(vm_clock) - ohci->sof_time; tks = qemu_get_clock_ns(vm_clock) - ohci->sof_time;
/* avoid muldiv if possible */ /* avoid muldiv if possible */
if (tks >= usb_frame_time) if (tks >= usb_frame_time)

6
hw/usb-uhci.c
View file

@ -441,7 +441,7 @@ static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
case 0x00: case 0x00:
if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
/* start frame processing */ /* start frame processing */
qemu_mod_timer(s->frame_timer, qemu_get_clock(vm_clock)); qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
s->status &= ~UHCI_STS_HCHALTED; s->status &= ~UHCI_STS_HCHALTED;
} else if (!(val & UHCI_CMD_RS)) { } else if (!(val & UHCI_CMD_RS)) {
s->status |= UHCI_STS_HCHALTED; s->status |= UHCI_STS_HCHALTED;
@ -1133,8 +1133,8 @@ static int usb_uhci_common_initfn(UHCIState *s)
USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
usb_port_location(&s->ports[i].port, NULL, i+1); usb_port_location(&s->ports[i].port, NULL, i+1);
} }
s->frame_timer = qemu_new_timer(vm_clock, uhci_frame_timer, s); s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s);
s->expire_time = qemu_get_clock(vm_clock) + s->expire_time = qemu_get_clock_ns(vm_clock) +
(get_ticks_per_sec() / FRAME_TIMER_FREQ); (get_ticks_per_sec() / FRAME_TIMER_FREQ);
s->num_ports_vmstate = NB_PORTS; s->num_ports_vmstate = NB_PORTS;

2
hw/vga.c
View file

@ -260,7 +260,7 @@ static uint8_t vga_precise_retrace(VGACommonState *s)
int cur_line, cur_line_char, cur_char; int cur_line, cur_line_char, cur_char;
int64_t cur_tick; int64_t cur_tick;
cur_tick = qemu_get_clock(vm_clock); cur_tick = qemu_get_clock_ns(vm_clock);
cur_char = (cur_tick / r->ticks_per_char) % r->total_chars; cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
cur_line = cur_char / r->htotal; cur_line = cur_char / r->htotal;

6
hw/virtio-net.c
View file

@ -150,7 +150,7 @@ static void virtio_net_set_status(struct VirtIODevice *vdev, uint8_t status)
if (virtio_net_started(n, status) && !n->vhost_started) { if (virtio_net_started(n, status) && !n->vhost_started) {
if (n->tx_timer) { if (n->tx_timer) {
qemu_mod_timer(n->tx_timer, qemu_mod_timer(n->tx_timer,
qemu_get_clock(vm_clock) + n->tx_timeout); qemu_get_clock_ns(vm_clock) + n->tx_timeout);
} else { } else {
qemu_bh_schedule(n->tx_bh); qemu_bh_schedule(n->tx_bh);
} }
@ -785,7 +785,7 @@ static void virtio_net_handle_tx_timer(VirtIODevice *vdev, VirtQueue *vq)
virtio_net_flush_tx(n, vq); virtio_net_flush_tx(n, vq);
} else { } else {
qemu_mod_timer(n->tx_timer, qemu_mod_timer(n->tx_timer,
qemu_get_clock(vm_clock) + n->tx_timeout); qemu_get_clock_ns(vm_clock) + n->tx_timeout);
n->tx_waiting = 1; n->tx_waiting = 1;
virtio_queue_set_notification(vq, 0); virtio_queue_set_notification(vq, 0);
} }
@ -1019,7 +1019,7 @@ VirtIODevice *virtio_net_init(DeviceState *dev, NICConf *conf,
if (net->tx && !strcmp(net->tx, "timer")) { if (net->tx && !strcmp(net->tx, "timer")) {
n->tx_vq = virtio_add_queue(&n->vdev, 256, virtio_net_handle_tx_timer); n->tx_vq = virtio_add_queue(&n->vdev, 256, virtio_net_handle_tx_timer);
n->tx_timer = qemu_new_timer(vm_clock, virtio_net_tx_timer, n); n->tx_timer = qemu_new_timer_ns(vm_clock, virtio_net_tx_timer, n);
n->tx_timeout = net->txtimer; n->tx_timeout = net->txtimer;
} else { } else {
n->tx_vq = virtio_add_queue(&n->vdev, 256, virtio_net_handle_tx_bh); n->tx_vq = virtio_add_queue(&n->vdev, 256, virtio_net_handle_tx_bh);

8
hw/vt82c686.c
View file

@ -186,7 +186,7 @@ typedef struct VT686MC97State {
static uint32_t get_pmtmr(VT686PMState *s) static uint32_t get_pmtmr(VT686PMState *s)
{ {
uint32_t d; uint32_t d;
d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec()); d = muldiv64(qemu_get_clock_ns(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
return d & 0xffffff; return d & 0xffffff;
} }
@ -195,7 +195,7 @@ static int get_pmsts(VT686PMState *s)
int64_t d; int64_t d;
int pmsts; int pmsts;
pmsts = s->pmsts; pmsts = s->pmsts;
d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec()); d = muldiv64(qemu_get_clock_ns(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
if (d >= s->tmr_overflow_time) if (d >= s->tmr_overflow_time)
s->pmsts |= TMROF_EN; s->pmsts |= TMROF_EN;
return pmsts; return pmsts;
@ -238,7 +238,7 @@ static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
pmsts = get_pmsts(s); pmsts = get_pmsts(s);
if (pmsts & val & TMROF_EN) { if (pmsts & val & TMROF_EN) {
/* if TMRSTS is reset, then compute the new overflow time */ /* if TMRSTS is reset, then compute the new overflow time */
d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec()); d = muldiv64(qemu_get_clock_ns(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL; s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
} }
s->pmsts &= ~val; s->pmsts &= ~val;
@ -486,7 +486,7 @@ static int vt82c686b_pm_initfn(PCIDevice *dev)
apm_init(&s->apm, NULL, s); apm_init(&s->apm, NULL, s);
s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s); s->tmr_timer = qemu_new_timer_ns(vm_clock, pm_tmr_timer, s);
pm_smbus_init(&s->dev.qdev, &s->smb); pm_smbus_init(&s->dev.qdev, &s->smb);

4
hw/wdt_i6300esb.c
View file

@ -129,7 +129,7 @@ static void i6300esb_restart_timer(I6300State *d, int stage)
i6300esb_debug("stage %d, timeout %" PRIi64 "\n", d->stage, timeout); i6300esb_debug("stage %d, timeout %" PRIi64 "\n", d->stage, timeout);
qemu_mod_timer(d->timer, qemu_get_clock(vm_clock) + timeout); qemu_mod_timer(d->timer, qemu_get_clock_ns(vm_clock) + timeout);
} }
/* This is called when the guest disables the watchdog. */ /* This is called when the guest disables the watchdog. */
@ -410,7 +410,7 @@ static int i6300esb_init(PCIDevice *dev)
i6300esb_debug("I6300State = %p\n", d); i6300esb_debug("I6300State = %p\n", d);
d->timer = qemu_new_timer(vm_clock, i6300esb_timer_expired, d); d->timer = qemu_new_timer_ns(vm_clock, i6300esb_timer_expired, d);
d->previous_reboot_flag = 0; d->previous_reboot_flag = 0;
pci_conf = d->dev.config; pci_conf = d->dev.config;

4
hw/wdt_ib700.c
View file

@ -58,7 +58,7 @@ static void ib700_write_enable_reg(void *vp, uint32_t addr, uint32_t data)
ib700_debug("addr = %x, data = %x\n", addr, data); ib700_debug("addr = %x, data = %x\n", addr, data);
timeout = (int64_t) time_map[data & 0xF] * get_ticks_per_sec(); timeout = (int64_t) time_map[data & 0xF] * get_ticks_per_sec();
qemu_mod_timer(s->timer, qemu_get_clock (vm_clock) + timeout); qemu_mod_timer(s->timer, qemu_get_clock_ns (vm_clock) + timeout);
} }
/* A write (of any value) to this register disables the timer. */ /* A write (of any value) to this register disables the timer. */
@ -99,7 +99,7 @@ static int wdt_ib700_init(ISADevice *dev)
ib700_debug("watchdog init\n"); ib700_debug("watchdog init\n");
s->timer = qemu_new_timer(vm_clock, ib700_timer_expired, s); s->timer = qemu_new_timer_ns(vm_clock, ib700_timer_expired, s);
register_ioport_write(0x441, 2, 1, ib700_write_disable_reg, s); register_ioport_write(0x441, 2, 1, ib700_write_disable_reg, s);
register_ioport_write(0x443, 2, 1, ib700_write_enable_reg, s); register_ioport_write(0x443, 2, 1, ib700_write_enable_reg, s);

6
hw/xen_domainbuild.c
View file

@ -149,7 +149,7 @@ static void xen_domain_poll(void *opaque)
goto quit; goto quit;
} }
qemu_mod_timer(xen_poll, qemu_get_clock(rt_clock) + 1000); qemu_mod_timer(xen_poll, qemu_get_clock_ms(rt_clock) + 1000);
return; return;
quit: quit:
@ -291,8 +291,8 @@ int xen_domain_build_pv(const char *kernel, const char *ramdisk,
goto err; goto err;
} }
xen_poll = qemu_new_timer(rt_clock, xen_domain_poll, NULL); xen_poll = qemu_new_timer_ms(rt_clock, xen_domain_poll, NULL);
qemu_mod_timer(xen_poll, qemu_get_clock(rt_clock) + 1000); qemu_mod_timer(xen_poll, qemu_get_clock_ms(rt_clock) + 1000);
return 0; return 0;
err: err:

4
monitor.c
View file

@ -1873,7 +1873,7 @@ static void do_sendkey(Monitor *mon, const QDict *qdict)
kbd_put_keycode(keycode & 0x7f); kbd_put_keycode(keycode & 0x7f);
} }
/* delayed key up events */ /* delayed key up events */
qemu_mod_timer(key_timer, qemu_get_clock(vm_clock) + qemu_mod_timer(key_timer, qemu_get_clock_ns(vm_clock) +
muldiv64(get_ticks_per_sec(), hold_time, 1000)); muldiv64(get_ticks_per_sec(), hold_time, 1000));
} }
@ -5157,7 +5157,7 @@ void monitor_init(CharDriverState *chr, int flags)
Monitor *mon; Monitor *mon;
if (is_first_init) { if (is_first_init) {
key_timer = qemu_new_timer(vm_clock, release_keys, NULL); key_timer = qemu_new_timer_ns(vm_clock, release_keys, NULL);
is_first_init = 0; is_first_init = 0;
} }

2
net/dump.c
View file

@ -67,7 +67,7 @@ static ssize_t dump_receive(VLANClientState *nc, const uint8_t *buf, size_t size
return size; return size;
} }
ts = muldiv64(qemu_get_clock(vm_clock), 1000000, get_ticks_per_sec()); ts = muldiv64(qemu_get_clock_ns(vm_clock), 1000000, get_ticks_per_sec());
caplen = size > s->pcap_caplen ? s->pcap_caplen : size; caplen = size > s->pcap_caplen ? s->pcap_caplen : size;
hdr.ts.tv_sec = ts / 1000000; hdr.ts.tv_sec = ts / 1000000;

8
qemu-char.c
View file

@ -267,7 +267,7 @@ static int mux_chr_write(CharDriverState *chr, const uint8_t *buf, int len)
int64_t ti; int64_t ti;
int secs; int secs;
ti = qemu_get_clock(rt_clock); ti = qemu_get_clock_ms(rt_clock);
if (d->timestamps_start == -1) if (d->timestamps_start == -1)
d->timestamps_start = ti; d->timestamps_start = ti;
ti -= d->timestamps_start; ti -= d->timestamps_start;
@ -911,7 +911,7 @@ static void pty_chr_update_read_handler(CharDriverState *chr)
* timeout to the normal (much longer) poll interval before the * timeout to the normal (much longer) poll interval before the
* timer triggers. * timer triggers.
*/ */
qemu_mod_timer(s->timer, qemu_get_clock(rt_clock) + 10); qemu_mod_timer(s->timer, qemu_get_clock_ms(rt_clock) + 10);
} }
static void pty_chr_state(CharDriverState *chr, int connected) static void pty_chr_state(CharDriverState *chr, int connected)
@ -925,7 +925,7 @@ static void pty_chr_state(CharDriverState *chr, int connected)
/* (re-)connect poll interval for idle guests: once per second. /* (re-)connect poll interval for idle guests: once per second.
* We check more frequently in case the guests sends data to * We check more frequently in case the guests sends data to
* the virtual device linked to our pty. */ * the virtual device linked to our pty. */
qemu_mod_timer(s->timer, qemu_get_clock(rt_clock) + 1000); qemu_mod_timer(s->timer, qemu_get_clock_ms(rt_clock) + 1000);
} else { } else {
if (!s->connected) if (!s->connected)
qemu_chr_generic_open(chr); qemu_chr_generic_open(chr);
@ -1001,7 +1001,7 @@ static CharDriverState *qemu_chr_open_pty(QemuOpts *opts)
chr->chr_update_read_handler = pty_chr_update_read_handler; chr->chr_update_read_handler = pty_chr_update_read_handler;
chr->chr_close = pty_chr_close; chr->chr_close = pty_chr_close;
s->timer = qemu_new_timer(rt_clock, pty_chr_timer, chr); s->timer = qemu_new_timer_ms(rt_clock, pty_chr_timer, chr);
return chr; return chr;
} }

60
qemu-timer.c
View file

@ -153,12 +153,12 @@ void cpu_disable_ticks(void)
struct QEMUClock { struct QEMUClock {
int type; int type;
int enabled; int enabled;
/* XXX: add frequency */
}; };
struct QEMUTimer { struct QEMUTimer {
QEMUClock *clock; QEMUClock *clock;
int64_t expire_time; int64_t expire_time; /* in nanoseconds */
int scale;
QEMUTimerCB *cb; QEMUTimerCB *cb;
void *opaque; void *opaque;
struct QEMUTimer *next; struct QEMUTimer *next;
@ -242,7 +242,7 @@ static void icount_adjust(void)
return; return;
cur_time = cpu_get_clock(); cur_time = cpu_get_clock();
cur_icount = qemu_get_clock(vm_clock); cur_icount = qemu_get_clock_ns(vm_clock);
delta = cur_icount - cur_time; delta = cur_icount - cur_time;
/* FIXME: This is a very crude algorithm, somewhat prone to oscillation. */ /* FIXME: This is a very crude algorithm, somewhat prone to oscillation. */
if (delta > 0 if (delta > 0
@ -264,14 +264,14 @@ static void icount_adjust(void)
static void icount_adjust_rt(void * opaque) static void icount_adjust_rt(void * opaque)
{ {
qemu_mod_timer(icount_rt_timer, qemu_mod_timer(icount_rt_timer,
qemu_get_clock(rt_clock) + 1000); qemu_get_clock_ms(rt_clock) + 1000);
icount_adjust(); icount_adjust();
} }
static void icount_adjust_vm(void * opaque) static void icount_adjust_vm(void * opaque)
{ {
qemu_mod_timer(icount_vm_timer, qemu_mod_timer(icount_vm_timer,
qemu_get_clock(vm_clock) + get_ticks_per_sec() / 10); qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 10);
icount_adjust(); icount_adjust();
} }
@ -386,7 +386,8 @@ void qemu_clock_enable(QEMUClock *clock, int enabled)
clock->enabled = enabled; clock->enabled = enabled;
} }
QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque) QEMUTimer *qemu_new_timer(QEMUClock *clock, int scale,
QEMUTimerCB *cb, void *opaque)
{ {
QEMUTimer *ts; QEMUTimer *ts;
@ -394,6 +395,7 @@ QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque)
ts->clock = clock; ts->clock = clock;
ts->cb = cb; ts->cb = cb;
ts->opaque = opaque; ts->opaque = opaque;
ts->scale = scale;
return ts; return ts;
} }
@ -424,7 +426,7 @@ void qemu_del_timer(QEMUTimer *ts)
/* modify the current timer so that it will be fired when current_time /* modify the current timer so that it will be fired when current_time
>= expire_time. The corresponding callback will be called. */ >= expire_time. The corresponding callback will be called. */
void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time) static void qemu_mod_timer_ns(QEMUTimer *ts, int64_t expire_time)
{ {
QEMUTimer **pt, *t; QEMUTimer **pt, *t;
@ -457,6 +459,13 @@ void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time)
} }
} }
/* modify the current timer so that it will be fired when current_time
>= expire_time. The corresponding callback will be called. */
void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time)
{
qemu_mod_timer_ns(ts, expire_time * ts->scale);
}
int qemu_timer_pending(QEMUTimer *ts) int qemu_timer_pending(QEMUTimer *ts)
{ {
QEMUTimer *t; QEMUTimer *t;
@ -471,7 +480,7 @@ int qemu_timer_expired(QEMUTimer *timer_head, int64_t current_time)
{ {
if (!timer_head) if (!timer_head)
return 0; return 0;
return (timer_head->expire_time <= current_time); return (timer_head->expire_time <= current_time * timer_head->scale);
} }
static void qemu_run_timers(QEMUClock *clock) static void qemu_run_timers(QEMUClock *clock)
@ -482,7 +491,7 @@ static void qemu_run_timers(QEMUClock *clock)
if (!clock->enabled) if (!clock->enabled)
return; return;
current_time = qemu_get_clock (clock); current_time = qemu_get_clock_ns(clock);
ptimer_head = &active_timers[clock->type]; ptimer_head = &active_timers[clock->type];
for(;;) { for(;;) {
ts = *ptimer_head; ts = *ptimer_head;
@ -497,23 +506,6 @@ static void qemu_run_timers(QEMUClock *clock)
} }
} }
int64_t qemu_get_clock(QEMUClock *clock)
{
switch(clock->type) {
case QEMU_CLOCK_REALTIME:
return get_clock() / 1000000;
default:
case QEMU_CLOCK_VIRTUAL:
if (use_icount) {
return cpu_get_icount();
} else {
return cpu_get_clock();
}
case QEMU_CLOCK_HOST:
return get_clock_realtime();
}
}
int64_t qemu_get_clock_ns(QEMUClock *clock) int64_t qemu_get_clock_ns(QEMUClock *clock)
{ {
switch(clock->type) { switch(clock->type) {
@ -559,7 +551,7 @@ void qemu_get_timer(QEMUFile *f, QEMUTimer *ts)
expire_time = qemu_get_be64(f); expire_time = qemu_get_be64(f);
if (expire_time != -1) { if (expire_time != -1) {
qemu_mod_timer(ts, expire_time); qemu_mod_timer_ns(ts, expire_time);
} else { } else {
qemu_del_timer(ts); qemu_del_timer(ts);
} }
@ -601,12 +593,12 @@ void configure_icount(const char *option)
the virtual time trigger catches emulated time passing too fast. the virtual time trigger catches emulated time passing too fast.
Realtime triggers occur even when idle, so use them less frequently Realtime triggers occur even when idle, so use them less frequently
than VM triggers. */ than VM triggers. */
icount_rt_timer = qemu_new_timer(rt_clock, icount_adjust_rt, NULL); icount_rt_timer = qemu_new_timer_ms(rt_clock, icount_adjust_rt, NULL);
qemu_mod_timer(icount_rt_timer, qemu_mod_timer(icount_rt_timer,
qemu_get_clock(rt_clock) + 1000); qemu_get_clock_ms(rt_clock) + 1000);
icount_vm_timer = qemu_new_timer(vm_clock, icount_adjust_vm, NULL); icount_vm_timer = qemu_new_timer_ns(vm_clock, icount_adjust_vm, NULL);
qemu_mod_timer(icount_vm_timer, qemu_mod_timer(icount_vm_timer,
qemu_get_clock(vm_clock) + get_ticks_per_sec() / 10); qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 10);
} }
void qemu_run_all_timers(void) void qemu_run_all_timers(void)
@ -646,7 +638,7 @@ static void host_alarm_handler(int host_signum)
static int64_t delta_min = INT64_MAX; static int64_t delta_min = INT64_MAX;
static int64_t delta_max, delta_cum, last_clock, delta, ti; static int64_t delta_max, delta_cum, last_clock, delta, ti;
static int count; static int count;
ti = qemu_get_clock(vm_clock); ti = qemu_get_clock_ns(vm_clock);
if (last_clock != 0) { if (last_clock != 0) {
delta = ti - last_clock; delta = ti - last_clock;
if (delta < delta_min) if (delta < delta_min)
@ -706,7 +698,7 @@ static int64_t qemu_next_alarm_deadline(void)
if (!use_icount && active_timers[QEMU_CLOCK_VIRTUAL]) { if (!use_icount && active_timers[QEMU_CLOCK_VIRTUAL]) {
delta = active_timers[QEMU_CLOCK_VIRTUAL]->expire_time - delta = active_timers[QEMU_CLOCK_VIRTUAL]->expire_time -
qemu_get_clock(vm_clock); qemu_get_clock_ns(vm_clock);
} else { } else {
delta = INT32_MAX; delta = INT32_MAX;
} }
@ -717,7 +709,7 @@ static int64_t qemu_next_alarm_deadline(void)
delta = hdelta; delta = hdelta;
} }
if (active_timers[QEMU_CLOCK_REALTIME]) { if (active_timers[QEMU_CLOCK_REALTIME]) {
rtdelta = (active_timers[QEMU_CLOCK_REALTIME]->expire_time * 1000000 - rtdelta = (active_timers[QEMU_CLOCK_REALTIME]->expire_time -
qemu_get_clock_ns(rt_clock)); qemu_get_clock_ns(rt_clock));
if (rtdelta < delta) if (rtdelta < delta)
delta = rtdelta; delta = rtdelta;

25
qemu-timer.h
View file

@ -12,6 +12,10 @@
/* timers */ /* timers */
#define SCALE_MS 1000000
#define SCALE_US 1000
#define SCALE_NS 1
typedef struct QEMUClock QEMUClock; typedef struct QEMUClock QEMUClock;
typedef void QEMUTimerCB(void *opaque); typedef void QEMUTimerCB(void *opaque);
@ -33,11 +37,11 @@ extern QEMUClock *vm_clock;
the virtual clock. */ the virtual clock. */
extern QEMUClock *host_clock; extern QEMUClock *host_clock;
int64_t qemu_get_clock(QEMUClock *clock);
int64_t qemu_get_clock_ns(QEMUClock *clock); int64_t qemu_get_clock_ns(QEMUClock *clock);
void qemu_clock_enable(QEMUClock *clock, int enabled); void qemu_clock_enable(QEMUClock *clock, int enabled);
QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque); QEMUTimer *qemu_new_timer(QEMUClock *clock, int scale,
QEMUTimerCB *cb, void *opaque);
void qemu_free_timer(QEMUTimer *ts); void qemu_free_timer(QEMUTimer *ts);
void qemu_del_timer(QEMUTimer *ts); void qemu_del_timer(QEMUTimer *ts);
void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time); void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
@ -54,6 +58,23 @@ void init_clocks(void);
int init_timer_alarm(void); int init_timer_alarm(void);
void quit_timers(void); void quit_timers(void);
static inline QEMUTimer *qemu_new_timer_ns(QEMUClock *clock, QEMUTimerCB *cb,
void *opaque)
{
return qemu_new_timer(clock, SCALE_NS, cb, opaque);
}
static inline QEMUTimer *qemu_new_timer_ms(QEMUClock *clock, QEMUTimerCB *cb,
void *opaque)
{
return qemu_new_timer(clock, SCALE_MS, cb, opaque);
}
static inline int64_t qemu_get_clock_ms(QEMUClock *clock)
{
return qemu_get_clock_ns(clock) / SCALE_MS;
}
static inline int64_t get_ticks_per_sec(void) static inline int64_t get_ticks_per_sec(void)
{ {
return 1000000000LL; return 1000000000LL;

6
savevm.c
View file

@ -137,7 +137,7 @@ static void qemu_announce_self_once(void *opaque)
if (--count) { if (--count) {
/* delay 50ms, 150ms, 250ms, ... */ /* delay 50ms, 150ms, 250ms, ... */
qemu_mod_timer(timer, qemu_get_clock(rt_clock) + qemu_mod_timer(timer, qemu_get_clock_ms(rt_clock) +
50 + (SELF_ANNOUNCE_ROUNDS - count - 1) * 100); 50 + (SELF_ANNOUNCE_ROUNDS - count - 1) * 100);
} else { } else {
qemu_del_timer(timer); qemu_del_timer(timer);
@ -148,7 +148,7 @@ static void qemu_announce_self_once(void *opaque)
void qemu_announce_self(void) void qemu_announce_self(void)
{ {
static QEMUTimer *timer; static QEMUTimer *timer;
timer = qemu_new_timer(rt_clock, qemu_announce_self_once, &timer); timer = qemu_new_timer_ms(rt_clock, qemu_announce_self_once, &timer);
qemu_announce_self_once(&timer); qemu_announce_self_once(&timer);
} }
@ -1943,7 +1943,7 @@ void do_savevm(Monitor *mon, const QDict *qdict)
sn->date_sec = tv.tv_sec; sn->date_sec = tv.tv_sec;
sn->date_nsec = tv.tv_usec * 1000; sn->date_nsec = tv.tv_usec * 1000;
#endif #endif
sn->vm_clock_nsec = qemu_get_clock(vm_clock); sn->vm_clock_nsec = qemu_get_clock_ns(vm_clock);
if (name) { if (name) {
ret = bdrv_snapshot_find(bs, old_sn, name); ret = bdrv_snapshot_find(bs, old_sn, name);

2
slirp/slirp.c
View file

@ -393,7 +393,7 @@ void slirp_select_poll(fd_set *readfds, fd_set *writefds, fd_set *xfds,
global_writefds = writefds; global_writefds = writefds;
global_xfds = xfds; global_xfds = xfds;
curtime = qemu_get_clock(rt_clock); curtime = qemu_get_clock_ms(rt_clock);
QTAILQ_FOREACH(slirp, &slirp_instances, entry) { QTAILQ_FOREACH(slirp, &slirp_instances, entry) {
/* /*

4
target-ppc/kvm.c
View file

@ -85,7 +85,7 @@ int kvm_arch_init_vcpu(CPUState *cenv)
sregs.pvr = cenv->spr[SPR_PVR]; sregs.pvr = cenv->spr[SPR_PVR];
ret = kvm_vcpu_ioctl(cenv, KVM_SET_SREGS, &sregs); ret = kvm_vcpu_ioctl(cenv, KVM_SET_SREGS, &sregs);
idle_timer = qemu_new_timer(vm_clock, kvm_kick_env, cenv); idle_timer = qemu_new_timer_ns(vm_clock, kvm_kick_env, cenv);
return ret; return ret;
} }
@ -246,7 +246,7 @@ int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
printf("cpu %d fail inject %x\n", env->cpu_index, irq); printf("cpu %d fail inject %x\n", env->cpu_index, irq);
/* Always wake up soon in case the interrupt was level based */ /* Always wake up soon in case the interrupt was level based */
qemu_mod_timer(idle_timer, qemu_get_clock(vm_clock) + qemu_mod_timer(idle_timer, qemu_get_clock_ns(vm_clock) +
(get_ticks_per_sec() / 50)); (get_ticks_per_sec() / 50));
} }

6
target-ppc/kvm_ppc.c
View file

@ -89,7 +89,7 @@ void kvmppc_fdt_update(void *fdt)
static void kvmppc_timer_hack(void *opaque) static void kvmppc_timer_hack(void *opaque)
{ {
qemu_service_io(); qemu_service_io();
qemu_mod_timer(kvmppc_timer, qemu_get_clock(vm_clock) + kvmppc_timer_rate); qemu_mod_timer(kvmppc_timer, qemu_get_clock_ns(vm_clock) + kvmppc_timer_rate);
} }
void kvmppc_init(void) void kvmppc_init(void)
@ -99,7 +99,7 @@ void kvmppc_init(void)
* run. So, until Qemu gains IO threads, we create this timer to ensure * run. So, until Qemu gains IO threads, we create this timer to ensure
* that the device model gets a chance to run. */ * that the device model gets a chance to run. */
kvmppc_timer_rate = get_ticks_per_sec() / 10; kvmppc_timer_rate = get_ticks_per_sec() / 10;
kvmppc_timer = qemu_new_timer(vm_clock, &kvmppc_timer_hack, NULL); kvmppc_timer = qemu_new_timer_ns(vm_clock, &kvmppc_timer_hack, NULL);
qemu_mod_timer(kvmppc_timer, qemu_get_clock(vm_clock) + kvmppc_timer_rate); qemu_mod_timer(kvmppc_timer, qemu_get_clock_ns(vm_clock) + kvmppc_timer_rate);
} }

4
ui/spice-core.c
View file

@ -55,14 +55,14 @@ static SpiceTimer *timer_add(SpiceTimerFunc func, void *opaque)
SpiceTimer *timer; SpiceTimer *timer;
timer = qemu_mallocz(sizeof(*timer)); timer = qemu_mallocz(sizeof(*timer));
timer->timer = qemu_new_timer(rt_clock, func, opaque); timer->timer = qemu_new_timer_ms(rt_clock, func, opaque);
QTAILQ_INSERT_TAIL(&timers, timer, next); QTAILQ_INSERT_TAIL(&timers, timer, next);
return timer; return timer;
} }
static void timer_start(SpiceTimer *timer, uint32_t ms) static void timer_start(SpiceTimer *timer, uint32_t ms)
{ {
qemu_mod_timer(timer->timer, qemu_get_clock(rt_clock) + ms); qemu_mod_timer(timer->timer, qemu_get_clock_ms(rt_clock) + ms);
} }
static void timer_cancel(SpiceTimer *timer) static void timer_cancel(SpiceTimer *timer)

10
ui/vnc.c
View file

@ -1875,8 +1875,8 @@ static int protocol_client_msg(VncState *vs, uint8_t *data, size_t len)
if (data[0] > 3) { if (data[0] > 3) {
vd->timer_interval = VNC_REFRESH_INTERVAL_BASE; vd->timer_interval = VNC_REFRESH_INTERVAL_BASE;
if (!qemu_timer_expired(vd->timer, qemu_get_clock(rt_clock) + vd->timer_interval)) if (!qemu_timer_expired(vd->timer, qemu_get_clock_ms(rt_clock) + vd->timer_interval))
qemu_mod_timer(vd->timer, qemu_get_clock(rt_clock) + vd->timer_interval); qemu_mod_timer(vd->timer, qemu_get_clock_ms(rt_clock) + vd->timer_interval);
} }
switch (data[0]) { switch (data[0]) {
@ -2441,7 +2441,7 @@ static void vnc_refresh(void *opaque)
if (vnc_trylock_display(vd)) { if (vnc_trylock_display(vd)) {
vd->timer_interval = VNC_REFRESH_INTERVAL_BASE; vd->timer_interval = VNC_REFRESH_INTERVAL_BASE;
qemu_mod_timer(vd->timer, qemu_get_clock(rt_clock) + qemu_mod_timer(vd->timer, qemu_get_clock_ms(rt_clock) +
vd->timer_interval); vd->timer_interval);
return; return;
} }
@ -2468,14 +2468,14 @@ static void vnc_refresh(void *opaque)
if (vd->timer_interval > VNC_REFRESH_INTERVAL_MAX) if (vd->timer_interval > VNC_REFRESH_INTERVAL_MAX)
vd->timer_interval = VNC_REFRESH_INTERVAL_MAX; vd->timer_interval = VNC_REFRESH_INTERVAL_MAX;
} }
qemu_mod_timer(vd->timer, qemu_get_clock(rt_clock) + vd->timer_interval); qemu_mod_timer(vd->timer, qemu_get_clock_ms(rt_clock) + vd->timer_interval);
} }
static void vnc_init_timer(VncDisplay *vd) static void vnc_init_timer(VncDisplay *vd)
{ {
vd->timer_interval = VNC_REFRESH_INTERVAL_BASE; vd->timer_interval = VNC_REFRESH_INTERVAL_BASE;
if (vd->timer == NULL && !QTAILQ_EMPTY(&vd->clients)) { if (vd->timer == NULL && !QTAILQ_EMPTY(&vd->clients)) {
vd->timer = qemu_new_timer(rt_clock, vnc_refresh, vd); vd->timer = qemu_new_timer_ms(rt_clock, vnc_refresh, vd);
vnc_dpy_resize(vd->ds); vnc_dpy_resize(vd->ds);
vnc_refresh(vd); vnc_refresh(vd);
} }

4
usb-linux.c
View file

@ -1535,12 +1535,12 @@ static void usb_host_auto_check(void *unused)
} }
if (!usb_auto_timer) { if (!usb_auto_timer) {
usb_auto_timer = qemu_new_timer(rt_clock, usb_host_auto_check, NULL); usb_auto_timer = qemu_new_timer_ms(rt_clock, usb_host_auto_check, NULL);
if (!usb_auto_timer) { if (!usb_auto_timer) {
return; return;
} }
} }
qemu_mod_timer(usb_auto_timer, qemu_get_clock(rt_clock) + 2000); qemu_mod_timer(usb_auto_timer, qemu_get_clock_ms(rt_clock) + 2000);
} }
/* /*

12
vl.c
View file

@ -1142,7 +1142,7 @@ static void gui_update(void *opaque)
interval = dcl->gui_timer_interval; interval = dcl->gui_timer_interval;
dcl = dcl->next; dcl = dcl->next;
} }
qemu_mod_timer(ds->gui_timer, interval + qemu_get_clock(rt_clock)); qemu_mod_timer(ds->gui_timer, interval + qemu_get_clock_ms(rt_clock));
} }
static void nographic_update(void *opaque) static void nographic_update(void *opaque)
@ -1150,7 +1150,7 @@ static void nographic_update(void *opaque)
uint64_t interval = GUI_REFRESH_INTERVAL; uint64_t interval = GUI_REFRESH_INTERVAL;
qemu_flush_coalesced_mmio_buffer(); qemu_flush_coalesced_mmio_buffer();
qemu_mod_timer(nographic_timer, interval + qemu_get_clock(rt_clock)); qemu_mod_timer(nographic_timer, interval + qemu_get_clock_ms(rt_clock));
} }
struct vm_change_state_entry { struct vm_change_state_entry {
@ -3089,15 +3089,15 @@ int main(int argc, char **argv, char **envp)
dcl = ds->listeners; dcl = ds->listeners;
while (dcl != NULL) { while (dcl != NULL) {
if (dcl->dpy_refresh != NULL) { if (dcl->dpy_refresh != NULL) {
ds->gui_timer = qemu_new_timer(rt_clock, gui_update, ds); ds->gui_timer = qemu_new_timer_ms(rt_clock, gui_update, ds);
qemu_mod_timer(ds->gui_timer, qemu_get_clock(rt_clock)); qemu_mod_timer(ds->gui_timer, qemu_get_clock_ms(rt_clock));
break; break;
} }
dcl = dcl->next; dcl = dcl->next;
} }
if (ds->gui_timer == NULL) { if (ds->gui_timer == NULL) {
nographic_timer = qemu_new_timer(rt_clock, nographic_update, NULL); nographic_timer = qemu_new_timer_ms(rt_clock, nographic_update, NULL);
qemu_mod_timer(nographic_timer, qemu_get_clock(rt_clock)); qemu_mod_timer(nographic_timer, qemu_get_clock_ms(rt_clock));
} }
text_consoles_set_display(ds); text_consoles_set_display(ds);