tcg: Tidy softmmu_template.h
Avoid a loop in the tlb_fill path; the fill will either succeed or generate an exception. Inline the slow_ld/st function; it was a complete copy of the main helper except for the actual cross-page unaligned code, and the compiler was inlining it anyway. Add unlikely markers optimizing for the most common case of simple tlb miss. Make sure the compiler can optimize away the unaligned paths for a 1 byte access. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
e25c3887e6
commit
aac1fb0576
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@ -54,10 +54,6 @@
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#define ADDR_READ addr_read
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#endif
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static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env,
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target_ulong addr,
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int mmu_idx,
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uintptr_t retaddr);
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static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
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hwaddr physaddr,
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target_ulong addr,
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@ -86,52 +82,67 @@ glue(glue(helper_ret_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env,
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target_ulong addr, int mmu_idx,
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uintptr_t retaddr)
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{
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DATA_TYPE res;
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int index;
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target_ulong tlb_addr;
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hwaddr ioaddr;
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int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
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uintptr_t haddr;
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/* test if there is match for unaligned or IO access */
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/* XXX: could done more in memory macro in a non portable way */
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index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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redo:
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tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
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if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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if (tlb_addr & ~TARGET_PAGE_MASK) {
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/* IO access */
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if ((addr & (DATA_SIZE - 1)) != 0)
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goto do_unaligned_access;
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ioaddr = env->iotlb[mmu_idx][index];
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res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
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} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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/* slow unaligned access (it spans two pages or IO) */
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do_unaligned_access:
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/* If the TLB entry is for a different page, reload and try again. */
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if ((addr & TARGET_PAGE_MASK)
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!= (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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#ifdef ALIGNED_ONLY
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if ((addr & (DATA_SIZE - 1)) != 0) {
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do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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#endif
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res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr,
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mmu_idx, retaddr);
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} else {
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/* unaligned/aligned access in the same page */
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uintptr_t addend;
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#ifdef ALIGNED_ONLY
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if ((addr & (DATA_SIZE - 1)) != 0) {
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do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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}
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#endif
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addend = env->tlb_table[mmu_idx][index].addend;
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res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(intptr_t)
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(addr + addend));
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}
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} else {
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#ifdef ALIGNED_ONLY
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if ((addr & (DATA_SIZE - 1)) != 0)
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do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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#endif
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tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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goto redo;
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tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
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}
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return res;
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/* Handle an IO access. */
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if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
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hwaddr ioaddr;
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if ((addr & (DATA_SIZE - 1)) != 0) {
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goto do_unaligned_access;
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}
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ioaddr = env->iotlb[mmu_idx][index];
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return glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
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}
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/* Handle slow unaligned access (it spans two pages or IO). */
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if (DATA_SIZE > 1
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&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
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>= TARGET_PAGE_SIZE)) {
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target_ulong addr1, addr2;
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DATA_TYPE res1, res2, res;
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unsigned shift;
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do_unaligned_access:
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#ifdef ALIGNED_ONLY
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do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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#endif
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addr1 = addr & ~(DATA_SIZE - 1);
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addr2 = addr1 + DATA_SIZE;
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res1 = glue(glue(helper_ret_ld, SUFFIX), MMUSUFFIX)(env, addr1,
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mmu_idx, retaddr);
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res2 = glue(glue(helper_ret_ld, SUFFIX), MMUSUFFIX)(env, addr2,
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mmu_idx, retaddr);
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shift = (addr & (DATA_SIZE - 1)) * 8;
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#ifdef TARGET_WORDS_BIGENDIAN
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res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
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#else
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res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
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#endif
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return res;
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}
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/* Handle aligned access or unaligned access in the same page. */
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#ifdef ALIGNED_ONLY
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if ((addr & (DATA_SIZE - 1)) != 0) {
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do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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}
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#endif
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haddr = addr + env->tlb_table[mmu_idx][index].addend;
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return glue(glue(ld, USUFFIX), _raw)((uint8_t *)haddr);
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}
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DATA_TYPE
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@ -142,66 +153,8 @@ glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
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GETPC_EXT());
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}
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/* handle all unaligned cases */
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static DATA_TYPE
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glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env,
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target_ulong addr,
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int mmu_idx,
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uintptr_t retaddr)
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{
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DATA_TYPE res, res1, res2;
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int index, shift;
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hwaddr ioaddr;
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target_ulong tlb_addr, addr1, addr2;
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index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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redo:
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tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
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if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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if (tlb_addr & ~TARGET_PAGE_MASK) {
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/* IO access */
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if ((addr & (DATA_SIZE - 1)) != 0)
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goto do_unaligned_access;
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ioaddr = env->iotlb[mmu_idx][index];
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res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
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} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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do_unaligned_access:
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/* slow unaligned access (it spans two pages) */
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addr1 = addr & ~(DATA_SIZE - 1);
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addr2 = addr1 + DATA_SIZE;
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res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr1,
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mmu_idx, retaddr);
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res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr2,
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mmu_idx, retaddr);
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shift = (addr & (DATA_SIZE - 1)) * 8;
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#ifdef TARGET_WORDS_BIGENDIAN
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res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
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#else
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res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
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#endif
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res = (DATA_TYPE)res;
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} else {
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/* unaligned/aligned access in the same page */
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uintptr_t addend = env->tlb_table[mmu_idx][index].addend;
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res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(intptr_t)
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(addr + addend));
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}
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} else {
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/* the page is not in the TLB : fill it */
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tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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goto redo;
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}
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return res;
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}
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#ifndef SOFTMMU_CODE_ACCESS
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static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
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target_ulong addr,
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DATA_TYPE val,
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int mmu_idx,
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uintptr_t retaddr);
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static inline void glue(io_write, SUFFIX)(CPUArchState *env,
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hwaddr physaddr,
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DATA_TYPE val,
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@ -225,48 +178,66 @@ glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
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target_ulong addr, DATA_TYPE val,
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int mmu_idx, uintptr_t retaddr)
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{
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hwaddr ioaddr;
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target_ulong tlb_addr;
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int index;
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int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
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uintptr_t haddr;
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index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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redo:
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tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
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if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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if (tlb_addr & ~TARGET_PAGE_MASK) {
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/* IO access */
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if ((addr & (DATA_SIZE - 1)) != 0)
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goto do_unaligned_access;
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ioaddr = env->iotlb[mmu_idx][index];
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glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
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} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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do_unaligned_access:
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/* If the TLB entry is for a different page, reload and try again. */
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if ((addr & TARGET_PAGE_MASK)
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!= (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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#ifdef ALIGNED_ONLY
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if ((addr & (DATA_SIZE - 1)) != 0) {
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do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
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#endif
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glue(glue(slow_st, SUFFIX), MMUSUFFIX)(env, addr, val,
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mmu_idx, retaddr);
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} else {
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/* aligned/unaligned access in the same page */
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uintptr_t addend;
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#ifdef ALIGNED_ONLY
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if ((addr & (DATA_SIZE - 1)) != 0) {
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do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
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}
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#endif
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addend = env->tlb_table[mmu_idx][index].addend;
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glue(glue(st, SUFFIX), _raw)((uint8_t *)(intptr_t)
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(addr + addend), val);
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}
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} else {
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/* the page is not in the TLB : fill it */
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#ifdef ALIGNED_ONLY
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if ((addr & (DATA_SIZE - 1)) != 0)
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do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
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#endif
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tlb_fill(env, addr, 1, mmu_idx, retaddr);
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goto redo;
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tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
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}
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/* Handle an IO access. */
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if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
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hwaddr ioaddr;
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if ((addr & (DATA_SIZE - 1)) != 0) {
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goto do_unaligned_access;
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}
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ioaddr = env->iotlb[mmu_idx][index];
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glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
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return;
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}
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/* Handle slow unaligned access (it spans two pages or IO). */
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if (DATA_SIZE > 1
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&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
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>= TARGET_PAGE_SIZE)) {
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int i;
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do_unaligned_access:
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#ifdef ALIGNED_ONLY
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do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
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#endif
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/* XXX: not efficient, but simple */
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/* Note: relies on the fact that tlb_fill() does not remove the
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* previous page from the TLB cache. */
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for (i = DATA_SIZE - 1; i >= 0; i--) {
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#ifdef TARGET_WORDS_BIGENDIAN
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uint8_t val8 = val >> (((DATA_SIZE - 1) * 8) - (i * 8));
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#else
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uint8_t val8 = val >> (i * 8);
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#endif
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glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
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mmu_idx, retaddr);
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}
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return;
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}
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/* Handle aligned access or unaligned access in the same page. */
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#ifdef ALIGNED_ONLY
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if ((addr & (DATA_SIZE - 1)) != 0) {
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do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
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}
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#endif
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haddr = addr + env->tlb_table[mmu_idx][index].addend;
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glue(glue(st, SUFFIX), _raw)((uint8_t *)haddr, val);
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}
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void
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@ -277,56 +248,6 @@ glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
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GETPC_EXT());
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}
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/* handles all unaligned cases */
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static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
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target_ulong addr,
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DATA_TYPE val,
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int mmu_idx,
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uintptr_t retaddr)
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{
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hwaddr ioaddr;
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target_ulong tlb_addr;
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int index, i;
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index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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redo:
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tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
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if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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if (tlb_addr & ~TARGET_PAGE_MASK) {
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/* IO access */
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if ((addr & (DATA_SIZE - 1)) != 0)
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goto do_unaligned_access;
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ioaddr = env->iotlb[mmu_idx][index];
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glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
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} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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do_unaligned_access:
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/* XXX: not efficient, but simple */
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/* Note: relies on the fact that tlb_fill() does not remove the
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* previous page from the TLB cache. */
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for(i = DATA_SIZE - 1; i >= 0; i--) {
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#ifdef TARGET_WORDS_BIGENDIAN
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glue(slow_stb, MMUSUFFIX)(env, addr + i,
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val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
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mmu_idx, retaddr);
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#else
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glue(slow_stb, MMUSUFFIX)(env, addr + i,
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val >> (i * 8),
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mmu_idx, retaddr);
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#endif
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}
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} else {
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/* aligned/unaligned access in the same page */
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uintptr_t addend = env->tlb_table[mmu_idx][index].addend;
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glue(glue(st, SUFFIX), _raw)((uint8_t *)(intptr_t)
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(addr + addend), val);
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}
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} else {
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/* the page is not in the TLB : fill it */
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tlb_fill(env, addr, 1, mmu_idx, retaddr);
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goto redo;
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}
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}
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#endif /* !defined(SOFTMMU_CODE_ACCESS) */
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#undef READ_ACCESS_TYPE
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