target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
Zve32f extension requires the scalar processor to implement the F extension and implement all vector floating-point instructions for floating-point operands with EEW=32 (i.e., no widening floating-point operations). Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220118014522.13613-14-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>staging
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da61f1256f
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@ -66,6 +66,17 @@ static bool require_scale_rvf(DisasContext *s)
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}
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}
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static bool require_zve32f(DisasContext *s)
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{
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/* RVV + Zve32f = RVV. */
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if (has_ext(s, RVV)) {
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return true;
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}
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/* Zve32f doesn't support FP64. (Section 18.2) */
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return s->ext_zve32f ? s->sew <= MO_32 : true;
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}
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static bool require_zve64f(DisasContext *s)
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{
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/* RVV + Zve64f = RVV. */
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@ -2229,6 +2240,7 @@ static bool opfvv_check(DisasContext *s, arg_rmrr *a)
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require_rvf(s) &&
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vext_check_isa_ill(s) &&
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vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm) &&
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require_zve32f(s) &&
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require_zve64f(s);
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}
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@ -2310,6 +2322,7 @@ static bool opfvf_check(DisasContext *s, arg_rmrr *a)
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require_rvf(s) &&
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vext_check_isa_ill(s) &&
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vext_check_ss(s, a->rd, a->rs2, a->vm) &&
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require_zve32f(s) &&
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require_zve64f(s);
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}
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@ -2532,6 +2545,7 @@ static bool opfv_check(DisasContext *s, arg_rmr *a)
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vext_check_isa_ill(s) &&
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/* OPFV instructions ignore vs1 check */
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vext_check_ss(s, a->rd, a->rs2, a->vm) &&
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require_zve32f(s) &&
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require_zve64f(s);
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}
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@ -2598,6 +2612,7 @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
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require_rvf(s) &&
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vext_check_isa_ill(s) &&
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vext_check_mss(s, a->rd, a->rs1, a->rs2) &&
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require_zve32f(s) &&
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require_zve64f(s);
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}
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@ -2612,6 +2627,7 @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
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require_rvf(s) &&
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vext_check_isa_ill(s) &&
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vext_check_ms(s, a->rd, a->rs2) &&
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require_zve32f(s) &&
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require_zve64f(s);
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}
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@ -2634,6 +2650,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
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require_rvf(s) &&
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vext_check_isa_ill(s) &&
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require_align(a->rd, s->lmul) &&
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require_zve32f(s) &&
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require_zve64f(s)) {
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gen_set_rm(s, RISCV_FRM_DYN);
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@ -3368,6 +3385,7 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
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if (require_rvv(s) &&
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require_rvf(s) &&
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vext_check_isa_ill(s) &&
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require_zve32f(s) &&
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require_zve64f(s)) {
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gen_set_rm(s, RISCV_FRM_DYN);
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@ -3395,6 +3413,7 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
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if (require_rvv(s) &&
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require_rvf(s) &&
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vext_check_isa_ill(s) &&
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require_zve32f(s) &&
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require_zve64f(s)) {
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gen_set_rm(s, RISCV_FRM_DYN);
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@ -3447,6 +3466,7 @@ static bool fslideup_check(DisasContext *s, arg_rmrr *a)
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{
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return slideup_check(s, a) &&
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require_rvf(s) &&
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require_zve32f(s) &&
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require_zve64f(s);
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}
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@ -3454,6 +3474,7 @@ static bool fslidedown_check(DisasContext *s, arg_rmrr *a)
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{
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return slidedown_check(s, a) &&
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require_rvf(s) &&
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require_zve32f(s) &&
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require_zve64f(s);
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}
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