target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness
Adjust the interface to match what has been done to the TCGv_i32 load/store functions. This is less obvious, because at present the only user of these functions, trans_VLDST_multiple, also wants to manipulate the endianness to speed up loading multiple bytes. Thus we retain an "internal" interface which is identical to the current gen_aa32_{ld,st}_i64 interface. The "new" interface will gain users as we remove the legacy interfaces, gen_aa32_ld64 and gen_aa32_st64. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210419202257.161730-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -494,11 +494,13 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
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int tt = a->vd + reg + spacing * xs;
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int tt = a->vd + reg + spacing * xs;
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if (a->l) {
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if (a->l) {
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gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size);
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gen_aa32_ld_internal_i64(s, tmp64, addr, mmu_idx,
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endian | size);
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neon_store_element64(tt, n, size, tmp64);
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neon_store_element64(tt, n, size, tmp64);
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} else {
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} else {
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neon_load_element64(tmp64, tt, n, size);
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neon_load_element64(tmp64, tt, n, size);
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gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size);
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gen_aa32_st_internal_i64(s, tmp64, addr, mmu_idx,
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endian | size);
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}
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}
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tcg_gen_add_i32(addr, addr, tmp);
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tcg_gen_add_i32(addr, addr, tmp);
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}
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}
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@ -949,6 +949,37 @@ static void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val,
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tcg_temp_free(addr);
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tcg_temp_free(addr);
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}
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}
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static void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val,
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TCGv_i32 a32, int index, MemOp opc)
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{
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TCGv addr = gen_aa32_addr(s, a32, opc);
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tcg_gen_qemu_ld_i64(val, addr, index, opc);
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/* Not needed for user-mode BE32, where we use MO_BE instead. */
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if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {
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tcg_gen_rotri_i64(val, val, 32);
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}
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tcg_temp_free(addr);
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}
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static void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val,
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TCGv_i32 a32, int index, MemOp opc)
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{
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TCGv addr = gen_aa32_addr(s, a32, opc);
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/* Not needed for user-mode BE32, where we use MO_BE instead. */
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if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {
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TCGv_i64 tmp = tcg_temp_new_i64();
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tcg_gen_rotri_i64(tmp, val, 32);
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tcg_gen_qemu_st_i64(tmp, addr, index, opc);
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tcg_temp_free_i64(tmp);
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} else {
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tcg_gen_qemu_st_i64(val, addr, index, opc);
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}
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tcg_temp_free(addr);
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}
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static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
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static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
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int index, MemOp opc)
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int index, MemOp opc)
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{
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{
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@ -961,6 +992,18 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
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gen_aa32_st_internal_i32(s, val, a32, index, finalize_memop(s, opc));
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gen_aa32_st_internal_i32(s, val, a32, index, finalize_memop(s, opc));
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}
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}
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static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
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int index, MemOp opc)
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{
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gen_aa32_ld_internal_i64(s, val, a32, index, finalize_memop(s, opc));
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}
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static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
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int index, MemOp opc)
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{
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gen_aa32_st_internal_i64(s, val, a32, index, finalize_memop(s, opc));
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}
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#define DO_GEN_LD(SUFF, OPC) \
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#define DO_GEN_LD(SUFF, OPC) \
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static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
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static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
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TCGv_i32 a32, int index) \
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TCGv_i32 a32, int index) \
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@ -975,47 +1018,16 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
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gen_aa32_st_i32(s, val, a32, index, OPC); \
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gen_aa32_st_i32(s, val, a32, index, OPC); \
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}
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}
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static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
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int index, MemOp opc)
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{
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TCGv addr = gen_aa32_addr(s, a32, opc);
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tcg_gen_qemu_ld_i64(val, addr, index, opc);
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/* Not needed for user-mode BE32, where we use MO_BE instead. */
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if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {
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tcg_gen_rotri_i64(val, val, 32);
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}
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tcg_temp_free(addr);
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}
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static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
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static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
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TCGv_i32 a32, int index)
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TCGv_i32 a32, int index)
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{
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{
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gen_aa32_ld_i64(s, val, a32, index, MO_Q | s->be_data);
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gen_aa32_ld_i64(s, val, a32, index, MO_Q);
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}
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static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
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int index, MemOp opc)
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{
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TCGv addr = gen_aa32_addr(s, a32, opc);
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/* Not needed for user-mode BE32, where we use MO_BE instead. */
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if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {
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TCGv_i64 tmp = tcg_temp_new_i64();
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tcg_gen_rotri_i64(tmp, val, 32);
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tcg_gen_qemu_st_i64(tmp, addr, index, opc);
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tcg_temp_free_i64(tmp);
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} else {
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tcg_gen_qemu_st_i64(val, addr, index, opc);
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}
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tcg_temp_free(addr);
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}
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}
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static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
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static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
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TCGv_i32 a32, int index)
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TCGv_i32 a32, int index)
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{
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{
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gen_aa32_st_i64(s, val, a32, index, MO_Q | s->be_data);
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gen_aa32_st_i64(s, val, a32, index, MO_Q);
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}
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}
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DO_GEN_LD(8u, MO_UB)
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DO_GEN_LD(8u, MO_UB)
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