MAC DBDMA: store register values in native endianness
Store the register values in native endianness, by dropping all the endianness conversion functions, and converting the endianness in dbdma_readl/dbdma_writel instead. Also guard the endianness conversion with TARGET_WORDS_BIGENDIAN to simulate the backward connection of the bus. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
parent
c84bd4f104
commit
ad674e53b5
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@ -184,19 +184,19 @@ static void dump_dbdma_cmd(dbdma_cmd *cmd)
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static void dbdma_cmdptr_load(DBDMA_channel *ch)
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static void dbdma_cmdptr_load(DBDMA_channel *ch)
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{
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{
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DBDMA_DPRINTF("dbdma_cmdptr_load 0x%08x\n",
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DBDMA_DPRINTF("dbdma_cmdptr_load 0x%08x\n",
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be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]));
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ch->regs[DBDMA_CMDPTR_LO]);
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cpu_physical_memory_read(be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]),
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cpu_physical_memory_read(ch->regs[DBDMA_CMDPTR_LO],
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(uint8_t*)&ch->current, sizeof(dbdma_cmd));
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(uint8_t*)&ch->current, sizeof(dbdma_cmd));
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}
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}
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static void dbdma_cmdptr_save(DBDMA_channel *ch)
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static void dbdma_cmdptr_save(DBDMA_channel *ch)
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{
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{
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DBDMA_DPRINTF("dbdma_cmdptr_save 0x%08x\n",
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DBDMA_DPRINTF("dbdma_cmdptr_save 0x%08x\n",
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be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]));
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ch->regs[DBDMA_CMDPTR_LO]);
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DBDMA_DPRINTF("xfer_status 0x%08x res_count 0x%04x\n",
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DBDMA_DPRINTF("xfer_status 0x%08x res_count 0x%04x\n",
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le16_to_cpu(ch->current.xfer_status),
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le16_to_cpu(ch->current.xfer_status),
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le16_to_cpu(ch->current.res_count));
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le16_to_cpu(ch->current.res_count));
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cpu_physical_memory_write(be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]),
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cpu_physical_memory_write(ch->regs[DBDMA_CMDPTR_LO],
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(uint8_t*)&ch->current, sizeof(dbdma_cmd));
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(uint8_t*)&ch->current, sizeof(dbdma_cmd));
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}
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}
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@ -204,8 +204,8 @@ static void kill_channel(DBDMA_channel *ch)
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{
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{
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DBDMA_DPRINTF("kill_channel\n");
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DBDMA_DPRINTF("kill_channel\n");
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ch->regs[DBDMA_STATUS] |= cpu_to_be32(DEAD);
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ch->regs[DBDMA_STATUS] |= DEAD;
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ch->regs[DBDMA_STATUS] &= cpu_to_be32(~ACTIVE);
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ch->regs[DBDMA_STATUS] &= ~ACTIVE;
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qemu_irq_raise(ch->irq);
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qemu_irq_raise(ch->irq);
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}
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}
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@ -230,10 +230,10 @@ static void conditional_interrupt(DBDMA_channel *ch)
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return;
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return;
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}
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}
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status = be32_to_cpu(ch->regs[DBDMA_STATUS]) & DEVSTAT;
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status = ch->regs[DBDMA_STATUS] & DEVSTAT;
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sel_mask = (be32_to_cpu(ch->regs[DBDMA_INTR_SEL]) >> 16) & 0x0f;
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sel_mask = (ch->regs[DBDMA_INTR_SEL] >> 16) & 0x0f;
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sel_value = be32_to_cpu(ch->regs[DBDMA_INTR_SEL]) & 0x0f;
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sel_value = ch->regs[DBDMA_INTR_SEL] & 0x0f;
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cond = (status & sel_mask) == (sel_value & sel_mask);
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cond = (status & sel_mask) == (sel_value & sel_mask);
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@ -268,10 +268,10 @@ static int conditional_wait(DBDMA_channel *ch)
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return 1;
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return 1;
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}
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}
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status = be32_to_cpu(ch->regs[DBDMA_STATUS]) & DEVSTAT;
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status = ch->regs[DBDMA_STATUS] & DEVSTAT;
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sel_mask = (be32_to_cpu(ch->regs[DBDMA_WAIT_SEL]) >> 16) & 0x0f;
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sel_mask = (ch->regs[DBDMA_WAIT_SEL] >> 16) & 0x0f;
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sel_value = be32_to_cpu(ch->regs[DBDMA_WAIT_SEL]) & 0x0f;
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sel_value = ch->regs[DBDMA_WAIT_SEL] & 0x0f;
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cond = (status & sel_mask) == (sel_value & sel_mask);
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cond = (status & sel_mask) == (sel_value & sel_mask);
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@ -292,10 +292,10 @@ static void next(DBDMA_channel *ch)
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{
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{
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uint32_t cp;
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uint32_t cp;
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ch->regs[DBDMA_STATUS] &= cpu_to_be32(~BT);
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ch->regs[DBDMA_STATUS] &= ~BT;
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cp = be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]);
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cp = ch->regs[DBDMA_CMDPTR_LO];
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ch->regs[DBDMA_CMDPTR_LO] = cpu_to_be32(cp + sizeof(dbdma_cmd));
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ch->regs[DBDMA_CMDPTR_LO] = cp + sizeof(dbdma_cmd);
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dbdma_cmdptr_load(ch);
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dbdma_cmdptr_load(ch);
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}
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}
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@ -304,7 +304,7 @@ static void branch(DBDMA_channel *ch)
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dbdma_cmd *current = &ch->current;
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dbdma_cmd *current = &ch->current;
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ch->regs[DBDMA_CMDPTR_LO] = current->cmd_dep;
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ch->regs[DBDMA_CMDPTR_LO] = current->cmd_dep;
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ch->regs[DBDMA_STATUS] |= cpu_to_be32(BT);
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ch->regs[DBDMA_STATUS] |= BT;
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dbdma_cmdptr_load(ch);
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dbdma_cmdptr_load(ch);
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}
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}
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@ -331,10 +331,10 @@ static void conditional_branch(DBDMA_channel *ch)
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return;
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return;
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}
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}
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status = be32_to_cpu(ch->regs[DBDMA_STATUS]) & DEVSTAT;
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status = ch->regs[DBDMA_STATUS] & DEVSTAT;
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sel_mask = (be32_to_cpu(ch->regs[DBDMA_BRANCH_SEL]) >> 16) & 0x0f;
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sel_mask = (ch->regs[DBDMA_BRANCH_SEL] >> 16) & 0x0f;
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sel_value = be32_to_cpu(ch->regs[DBDMA_BRANCH_SEL]) & 0x0f;
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sel_value = ch->regs[DBDMA_BRANCH_SEL] & 0x0f;
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cond = (status & sel_mask) == (sel_value & sel_mask);
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cond = (status & sel_mask) == (sel_value & sel_mask);
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@ -365,19 +365,19 @@ static void dbdma_end(DBDMA_io *io)
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if (conditional_wait(ch))
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if (conditional_wait(ch))
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goto wait;
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goto wait;
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current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
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current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]);
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current->res_count = cpu_to_le16(be32_to_cpu(io->len));
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current->res_count = cpu_to_le16(io->len);
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dbdma_cmdptr_save(ch);
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dbdma_cmdptr_save(ch);
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if (io->is_last)
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if (io->is_last)
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ch->regs[DBDMA_STATUS] &= cpu_to_be32(~FLUSH);
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ch->regs[DBDMA_STATUS] &= ~FLUSH;
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conditional_interrupt(ch);
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conditional_interrupt(ch);
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conditional_branch(ch);
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conditional_branch(ch);
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wait:
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wait:
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ch->processing = 0;
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ch->processing = 0;
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if ((ch->regs[DBDMA_STATUS] & cpu_to_be32(RUN)) &&
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if ((ch->regs[DBDMA_STATUS] & RUN) &&
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(ch->regs[DBDMA_STATUS] & cpu_to_be32(ACTIVE)))
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(ch->regs[DBDMA_STATUS] & ACTIVE))
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channel_run(ch);
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channel_run(ch);
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}
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}
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@ -456,9 +456,9 @@ static void load_word(DBDMA_channel *ch, int key, uint32_t addr,
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if (conditional_wait(ch))
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if (conditional_wait(ch))
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goto wait;
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goto wait;
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current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
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current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]);
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dbdma_cmdptr_save(ch);
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dbdma_cmdptr_save(ch);
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ch->regs[DBDMA_STATUS] &= cpu_to_be32(~FLUSH);
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ch->regs[DBDMA_STATUS] &= ~FLUSH;
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conditional_interrupt(ch);
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conditional_interrupt(ch);
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next(ch);
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next(ch);
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@ -494,9 +494,9 @@ static void store_word(DBDMA_channel *ch, int key, uint32_t addr,
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if (conditional_wait(ch))
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if (conditional_wait(ch))
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goto wait;
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goto wait;
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current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
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current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]);
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dbdma_cmdptr_save(ch);
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dbdma_cmdptr_save(ch);
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ch->regs[DBDMA_STATUS] &= cpu_to_be32(~FLUSH);
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ch->regs[DBDMA_STATUS] &= ~FLUSH;
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conditional_interrupt(ch);
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conditional_interrupt(ch);
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next(ch);
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next(ch);
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@ -512,7 +512,7 @@ static void nop(DBDMA_channel *ch)
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if (conditional_wait(ch))
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if (conditional_wait(ch))
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goto wait;
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goto wait;
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current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
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current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]);
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dbdma_cmdptr_save(ch);
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dbdma_cmdptr_save(ch);
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conditional_interrupt(ch);
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conditional_interrupt(ch);
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@ -524,7 +524,7 @@ wait:
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static void stop(DBDMA_channel *ch)
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static void stop(DBDMA_channel *ch)
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{
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{
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ch->regs[DBDMA_STATUS] &= cpu_to_be32(~(ACTIVE|DEAD|FLUSH));
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ch->regs[DBDMA_STATUS] &= ~(ACTIVE|DEAD|FLUSH);
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/* the stop command does not increment command pointer */
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/* the stop command does not increment command pointer */
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}
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}
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@ -541,7 +541,7 @@ static void channel_run(DBDMA_channel *ch)
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/* clear WAKE flag at command fetch */
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/* clear WAKE flag at command fetch */
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ch->regs[DBDMA_STATUS] &= cpu_to_be32(~WAKE);
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ch->regs[DBDMA_STATUS] &= ~WAKE;
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cmd = le16_to_cpu(current->command) & COMMAND_MASK;
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cmd = le16_to_cpu(current->command) & COMMAND_MASK;
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@ -618,7 +618,7 @@ static void DBDMA_run (DBDMA_channel *ch)
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int channel;
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int channel;
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for (channel = 0; channel < DBDMA_CHANNELS; channel++, ch++) {
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for (channel = 0; channel < DBDMA_CHANNELS; channel++, ch++) {
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uint32_t status = be32_to_cpu(ch->regs[DBDMA_STATUS]);
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uint32_t status = ch->regs[DBDMA_STATUS];
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if (!ch->processing && (status & RUN) && (status & ACTIVE))
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if (!ch->processing && (status & RUN) && (status & ACTIVE))
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channel_run(ch);
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channel_run(ch);
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}
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}
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@ -660,12 +660,12 @@ dbdma_control_write(DBDMA_channel *ch)
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uint16_t mask, value;
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uint16_t mask, value;
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uint32_t status;
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uint32_t status;
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mask = (be32_to_cpu(ch->regs[DBDMA_CONTROL]) >> 16) & 0xffff;
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mask = (ch->regs[DBDMA_CONTROL] >> 16) & 0xffff;
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value = be32_to_cpu(ch->regs[DBDMA_CONTROL]) & 0xffff;
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value = ch->regs[DBDMA_CONTROL] & 0xffff;
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value &= (RUN | PAUSE | FLUSH | WAKE | DEVSTAT);
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value &= (RUN | PAUSE | FLUSH | WAKE | DEVSTAT);
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status = be32_to_cpu(ch->regs[DBDMA_STATUS]);
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status = ch->regs[DBDMA_STATUS];
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status = (value & mask) | (status & ~mask);
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status = (value & mask) | (status & ~mask);
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@ -677,14 +677,14 @@ dbdma_control_write(DBDMA_channel *ch)
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}
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}
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if (status & PAUSE)
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if (status & PAUSE)
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status &= ~ACTIVE;
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status &= ~ACTIVE;
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if ((be32_to_cpu(ch->regs[DBDMA_STATUS]) & RUN) && !(status & RUN)) {
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if ((ch->regs[DBDMA_STATUS] & RUN) && !(status & RUN)) {
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/* RUN is cleared */
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/* RUN is cleared */
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status &= ~(ACTIVE|DEAD);
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status &= ~(ACTIVE|DEAD);
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}
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}
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DBDMA_DPRINTF(" status 0x%08x\n", status);
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DBDMA_DPRINTF(" status 0x%08x\n", status);
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ch->regs[DBDMA_STATUS] = cpu_to_be32(status);
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ch->regs[DBDMA_STATUS] = status;
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if (status & ACTIVE)
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if (status & ACTIVE)
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qemu_bh_schedule(dbdma_bh);
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qemu_bh_schedule(dbdma_bh);
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@ -703,10 +703,14 @@ static void dbdma_writel (void *opaque,
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DBDMA_DPRINTF("channel 0x%x reg 0x%x\n",
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DBDMA_DPRINTF("channel 0x%x reg 0x%x\n",
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(uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg);
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(uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg);
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap32(value);
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#endif
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/* cmdptr cannot be modified if channel is RUN or ACTIVE */
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/* cmdptr cannot be modified if channel is RUN or ACTIVE */
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if (reg == DBDMA_CMDPTR_LO &&
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if (reg == DBDMA_CMDPTR_LO &&
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(ch->regs[DBDMA_STATUS] & cpu_to_be32(RUN | ACTIVE)))
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(ch->regs[DBDMA_STATUS] & (RUN | ACTIVE)))
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return;
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return;
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ch->regs[reg] = value;
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ch->regs[reg] = value;
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@ -717,7 +721,7 @@ static void dbdma_writel (void *opaque,
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break;
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break;
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case DBDMA_CMDPTR_LO:
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case DBDMA_CMDPTR_LO:
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/* 16-byte aligned */
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/* 16-byte aligned */
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ch->regs[DBDMA_CMDPTR_LO] &= cpu_to_be32(~0xf);
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ch->regs[DBDMA_CMDPTR_LO] &= ~0xf;
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dbdma_cmdptr_load(ch);
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dbdma_cmdptr_load(ch);
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break;
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break;
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case DBDMA_STATUS:
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case DBDMA_STATUS:
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@ -782,6 +786,9 @@ static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr)
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break;
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break;
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}
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}
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap32(value);
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#endif
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return value;
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return value;
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}
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}
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