target/s390x: Remove leading underscores from #defines
We should not use leading underscores followed by a capital letter in #defines since such identifiers are reserved by the C standard. For ASCE_ORIGIN, REGION_ENTRY_ORIGIN and SEGMENT_ENTRY_ORIGIN I also added parentheses around the value to silence an error message from checkpatch.pl. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1520227018-4061-1-git-send-email-thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
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@ -538,39 +538,39 @@ typedef union SysIB {
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QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096);
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/* MMU defines */
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#define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
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#define _ASCE_SUBSPACE 0x200 /* subspace group control */
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#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
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#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
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#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
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#define _ASCE_REAL_SPACE 0x20 /* real space control */
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#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
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#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
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#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
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#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
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#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
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#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
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#define ASCE_ORIGIN (~0xfffULL) /* segment table origin */
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#define ASCE_SUBSPACE 0x200 /* subspace group control */
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#define ASCE_PRIVATE_SPACE 0x100 /* private space control */
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#define ASCE_ALT_EVENT 0x80 /* storage alteration event control */
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#define ASCE_SPACE_SWITCH 0x40 /* space switch event */
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#define ASCE_REAL_SPACE 0x20 /* real space control */
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#define ASCE_TYPE_MASK 0x0c /* asce table type mask */
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#define ASCE_TYPE_REGION1 0x0c /* region first table type */
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#define ASCE_TYPE_REGION2 0x08 /* region second table type */
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#define ASCE_TYPE_REGION3 0x04 /* region third table type */
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#define ASCE_TYPE_SEGMENT 0x00 /* segment table type */
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#define ASCE_TABLE_LENGTH 0x03 /* region table length */
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#define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
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#define _REGION_ENTRY_RO 0x200 /* region/segment protection bit */
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#define _REGION_ENTRY_TF 0xc0 /* region/segment table offset */
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#define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
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#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
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#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
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#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
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#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
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#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
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#define REGION_ENTRY_ORIGIN (~0xfffULL) /* region/segment table origin */
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#define REGION_ENTRY_RO 0x200 /* region/segment protection bit */
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#define REGION_ENTRY_TF 0xc0 /* region/segment table offset */
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#define REGION_ENTRY_INV 0x20 /* invalid region table entry */
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#define REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
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#define REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
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#define REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
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#define REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
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#define REGION_ENTRY_LENGTH 0x03 /* region third length */
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#define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
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#define _SEGMENT_ENTRY_FC 0x400 /* format control */
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#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
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#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
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#define SEGMENT_ENTRY_ORIGIN (~0x7ffULL) /* segment table origin */
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#define SEGMENT_ENTRY_FC 0x400 /* format control */
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#define SEGMENT_ENTRY_RO 0x200 /* page protection bit */
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#define SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
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#define VADDR_PX 0xff000 /* page index bits */
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#define VADDR_PX 0xff000 /* page index bits */
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#define _PAGE_RO 0x200 /* HW read-only bit */
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#define _PAGE_INVALID 0x400 /* HW invalid bit */
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#define _PAGE_RES0 0x800 /* bit must be zero */
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#define PAGE_RO 0x200 /* HW read-only bit */
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#define PAGE_INVALID 0x400 /* HW invalid bit */
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#define PAGE_RES0 0x800 /* bit must be zero */
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#define SK_C (0x1 << 1)
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#define SK_R (0x1 << 2)
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@ -1924,20 +1924,20 @@ void HELPER(idte)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint32_t m4)
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if (!(r2 & 0x800)) {
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/* invalidation-and-clearing operation */
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table = r1 & _ASCE_ORIGIN;
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table = r1 & ASCE_ORIGIN;
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entries = (r2 & 0x7ff) + 1;
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switch (r1 & _ASCE_TYPE_MASK) {
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case _ASCE_TYPE_REGION1:
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switch (r1 & ASCE_TYPE_MASK) {
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case ASCE_TYPE_REGION1:
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index = (r2 >> 53) & 0x7ff;
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break;
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case _ASCE_TYPE_REGION2:
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case ASCE_TYPE_REGION2:
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index = (r2 >> 42) & 0x7ff;
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break;
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case _ASCE_TYPE_REGION3:
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case ASCE_TYPE_REGION3:
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index = (r2 >> 31) & 0x7ff;
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break;
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case _ASCE_TYPE_SEGMENT:
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case ASCE_TYPE_SEGMENT:
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index = (r2 >> 20) & 0x7ff;
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break;
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}
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@ -1945,9 +1945,9 @@ void HELPER(idte)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint32_t m4)
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/* addresses are not wrapped in 24/31bit mode but table index is */
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raddr = table + ((index + i) & 0x7ff) * sizeof(entry);
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entry = cpu_ldq_real_ra(env, raddr, ra);
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if (!(entry & _REGION_ENTRY_INV)) {
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if (!(entry & REGION_ENTRY_INV)) {
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/* we are allowed to not store if already invalid */
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entry |= _REGION_ENTRY_INV;
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entry |= REGION_ENTRY_INV;
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cpu_stq_real_ra(env, raddr, entry, ra);
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}
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}
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@ -1971,12 +1971,12 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pto, uint64_t vaddr,
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uint64_t pte_addr, pte;
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/* Compute the page table entry address */
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pte_addr = (pto & _SEGMENT_ENTRY_ORIGIN);
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pte_addr = (pto & SEGMENT_ENTRY_ORIGIN);
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pte_addr += (vaddr & VADDR_PX) >> 9;
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/* Mark the page table entry as invalid */
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pte = cpu_ldq_real_ra(env, pte_addr, ra);
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pte |= _PAGE_INVALID;
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pte |= PAGE_INVALID;
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cpu_stq_real_ra(env, pte_addr, pte, ra);
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/* XXX we exploit the fact that Linux passes the exact virtual
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@ -128,11 +128,11 @@ static bool lowprot_enabled(const CPUS390XState *env, uint64_t asc)
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/* Check the private-space control bit */
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switch (asc) {
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case PSW_ASC_PRIMARY:
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return !(env->cregs[1] & _ASCE_PRIVATE_SPACE);
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return !(env->cregs[1] & ASCE_PRIVATE_SPACE);
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case PSW_ASC_SECONDARY:
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return !(env->cregs[7] & _ASCE_PRIVATE_SPACE);
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return !(env->cregs[7] & ASCE_PRIVATE_SPACE);
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case PSW_ASC_HOME:
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return !(env->cregs[13] & _ASCE_PRIVATE_SPACE);
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return !(env->cregs[13] & ASCE_PRIVATE_SPACE);
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default:
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/* We don't support access register mode */
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error_report("unsupported addressing mode");
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@ -159,20 +159,20 @@ static int mmu_translate_pte(CPUS390XState *env, target_ulong vaddr,
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uint64_t asc, uint64_t pt_entry,
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target_ulong *raddr, int *flags, int rw, bool exc)
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{
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if (pt_entry & _PAGE_INVALID) {
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if (pt_entry & PAGE_INVALID) {
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DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __func__, pt_entry);
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trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw, exc);
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return -1;
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}
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if (pt_entry & _PAGE_RES0) {
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if (pt_entry & PAGE_RES0) {
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trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw, exc);
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return -1;
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}
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if (pt_entry & _PAGE_RO) {
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if (pt_entry & PAGE_RO) {
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*flags &= ~PAGE_WRITE;
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}
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*raddr = pt_entry & _ASCE_ORIGIN;
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*raddr = pt_entry & ASCE_ORIGIN;
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PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __func__, pt_entry);
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@ -188,11 +188,11 @@ static int mmu_translate_segment(CPUS390XState *env, target_ulong vaddr,
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CPUState *cs = CPU(s390_env_get_cpu(env));
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uint64_t origin, offs, pt_entry;
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if (st_entry & _SEGMENT_ENTRY_RO) {
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if (st_entry & SEGMENT_ENTRY_RO) {
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*flags &= ~PAGE_WRITE;
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}
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if ((st_entry & _SEGMENT_ENTRY_FC) && (env->cregs[0] & CR0_EDAT)) {
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if ((st_entry & SEGMENT_ENTRY_FC) && (env->cregs[0] & CR0_EDAT)) {
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/* Decode EDAT1 segment frame absolute address (1MB page) */
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*raddr = (st_entry & 0xfffffffffff00000ULL) | (vaddr & 0xfffff);
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PTE_DPRINTF("%s: SEG=0x%" PRIx64 "\n", __func__, st_entry);
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@ -200,7 +200,7 @@ static int mmu_translate_segment(CPUS390XState *env, target_ulong vaddr,
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}
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/* Look up 4KB page entry */
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origin = st_entry & _SEGMENT_ENTRY_ORIGIN;
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origin = st_entry & SEGMENT_ENTRY_ORIGIN;
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offs = (vaddr & VADDR_PX) >> 9;
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pt_entry = ldq_phys(cs->as, origin + offs);
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PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
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@ -223,39 +223,39 @@ static int mmu_translate_region(CPUS390XState *env, target_ulong vaddr,
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PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, entry);
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origin = entry & _REGION_ENTRY_ORIGIN;
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origin = entry & REGION_ENTRY_ORIGIN;
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offs = (vaddr >> (17 + 11 * level / 4)) & 0x3ff8;
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new_entry = ldq_phys(cs->as, origin + offs);
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PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
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__func__, origin, offs, new_entry);
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if ((new_entry & _REGION_ENTRY_INV) != 0) {
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if ((new_entry & REGION_ENTRY_INV) != 0) {
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DPRINTF("%s: invalid region\n", __func__);
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trigger_page_fault(env, vaddr, pchks[level / 4], asc, rw, exc);
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return -1;
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}
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if ((new_entry & _REGION_ENTRY_TYPE_MASK) != level) {
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if ((new_entry & REGION_ENTRY_TYPE_MASK) != level) {
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trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw, exc);
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return -1;
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}
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if (level == _ASCE_TYPE_SEGMENT) {
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if (level == ASCE_TYPE_SEGMENT) {
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return mmu_translate_segment(env, vaddr, asc, new_entry, raddr, flags,
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rw, exc);
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}
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/* Check region table offset and length */
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offs = (vaddr >> (28 + 11 * (level - 4) / 4)) & 3;
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if (offs < ((new_entry & _REGION_ENTRY_TF) >> 6)
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|| offs > (new_entry & _REGION_ENTRY_LENGTH)) {
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if (offs < ((new_entry & REGION_ENTRY_TF) >> 6)
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|| offs > (new_entry & REGION_ENTRY_LENGTH)) {
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DPRINTF("%s: invalid offset or len (%lx)\n", __func__, new_entry);
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trigger_page_fault(env, vaddr, pchks[level / 4 - 1], asc, rw, exc);
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return -1;
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}
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if ((env->cregs[0] & CR0_EDAT) && (new_entry & _REGION_ENTRY_RO)) {
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if ((env->cregs[0] & CR0_EDAT) && (new_entry & REGION_ENTRY_RO)) {
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*flags &= ~PAGE_WRITE;
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}
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@ -271,52 +271,52 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
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int level;
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int r;
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if (asce & _ASCE_REAL_SPACE) {
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if (asce & ASCE_REAL_SPACE) {
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/* direct mapping */
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*raddr = vaddr;
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return 0;
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}
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level = asce & _ASCE_TYPE_MASK;
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level = asce & ASCE_TYPE_MASK;
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switch (level) {
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case _ASCE_TYPE_REGION1:
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if ((vaddr >> 62) > (asce & _ASCE_TABLE_LENGTH)) {
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case ASCE_TYPE_REGION1:
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if ((vaddr >> 62) > (asce & ASCE_TABLE_LENGTH)) {
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trigger_page_fault(env, vaddr, PGM_REG_FIRST_TRANS, asc, rw, exc);
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return -1;
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}
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break;
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case _ASCE_TYPE_REGION2:
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case ASCE_TYPE_REGION2:
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if (vaddr & 0xffe0000000000000ULL) {
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DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
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" 0xffe0000000000000ULL\n", __func__, vaddr);
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trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc);
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return -1;
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}
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if ((vaddr >> 51 & 3) > (asce & _ASCE_TABLE_LENGTH)) {
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if ((vaddr >> 51 & 3) > (asce & ASCE_TABLE_LENGTH)) {
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trigger_page_fault(env, vaddr, PGM_REG_SEC_TRANS, asc, rw, exc);
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return -1;
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}
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break;
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case _ASCE_TYPE_REGION3:
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case ASCE_TYPE_REGION3:
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if (vaddr & 0xfffffc0000000000ULL) {
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DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
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" 0xfffffc0000000000ULL\n", __func__, vaddr);
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trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc);
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return -1;
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}
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if ((vaddr >> 40 & 3) > (asce & _ASCE_TABLE_LENGTH)) {
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if ((vaddr >> 40 & 3) > (asce & ASCE_TABLE_LENGTH)) {
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trigger_page_fault(env, vaddr, PGM_REG_THIRD_TRANS, asc, rw, exc);
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return -1;
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}
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break;
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case _ASCE_TYPE_SEGMENT:
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case ASCE_TYPE_SEGMENT:
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if (vaddr & 0xffffffff80000000ULL) {
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DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
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" 0xffffffff80000000ULL\n", __func__, vaddr);
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trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc);
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return -1;
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}
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if ((vaddr >> 29 & 3) > (asce & _ASCE_TABLE_LENGTH)) {
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if ((vaddr >> 29 & 3) > (asce & ASCE_TABLE_LENGTH)) {
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trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw, exc);
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return -1;
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}
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