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target/arm: Diagnose UNPREDICTABLE ldrex/strex cases

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-23-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2019-09-04 12:30:12 -07:00 committed by Peter Maydell
parent 1efdd407a2
commit af28822899
1 changed files with 38 additions and 2 deletions
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40
target/arm/translate.c
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@ -8912,6 +8912,18 @@ static bool op_strex(DisasContext *s, arg_STREX *a, MemOp mop, bool rel)
{
TCGv_i32 addr;
/* We UNDEF for these UNPREDICTABLE cases. */
if (a->rd == 15 || a->rn == 15 || a->rt == 15
|| a->rd == a->rn || a->rd == a->rt
|| (s->thumb && (a->rd == 13 || a->rt == 13))
|| (mop == MO_64
&& (a->rt2 == 15
|| a->rd == a->rt2 || a->rt == a->rt2
|| (s->thumb && a->rt2 == 13)))) {
unallocated_encoding(s);
return true;
}
if (rel) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
}
@ -8938,6 +8950,7 @@ static bool trans_STREXD_a32(DisasContext *s, arg_STREX *a)
if (!ENABLE_ARCH_6K) {
return false;
}
/* We UNDEF for these UNPREDICTABLE cases. */
if (a->rt & 1) {
unallocated_encoding(s);
return true;
@ -8980,6 +8993,7 @@ static bool trans_STLEXD_a32(DisasContext *s, arg_STREX *a)
if (!ENABLE_ARCH_8) {
return false;
}
/* We UNDEF for these UNPREDICTABLE cases. */
if (a->rt & 1) {
unallocated_encoding(s);
return true;
@ -9019,8 +9033,13 @@ static bool op_stl(DisasContext *s, arg_STL *a, MemOp mop)
if (!ENABLE_ARCH_8) {
return false;
}
addr = load_reg(s, a->rn);
/* We UNDEF for these UNPREDICTABLE cases. */
if (a->rn == 15 || a->rt == 15) {
unallocated_encoding(s);
return true;
}
addr = load_reg(s, a->rn);
tmp = load_reg(s, a->rt);
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data);
@ -9050,6 +9069,16 @@ static bool op_ldrex(DisasContext *s, arg_LDREX *a, MemOp mop, bool acq)
{
TCGv_i32 addr;
/* We UNDEF for these UNPREDICTABLE cases. */
if (a->rn == 15 || a->rt == 15
|| (s->thumb && a->rt == 13)
|| (mop == MO_64
&& (a->rt2 == 15 || a->rt == a->rt2
|| (s->thumb && a->rt2 == 13)))) {
unallocated_encoding(s);
return true;
}
addr = tcg_temp_local_new_i32();
load_reg_var(s, addr, a->rn);
tcg_gen_addi_i32(addr, addr, a->imm);
@ -9076,6 +9105,7 @@ static bool trans_LDREXD_a32(DisasContext *s, arg_LDREX *a)
if (!ENABLE_ARCH_6K) {
return false;
}
/* We UNDEF for these UNPREDICTABLE cases. */
if (a->rt & 1) {
unallocated_encoding(s);
return true;
@ -9118,6 +9148,7 @@ static bool trans_LDAEXD_a32(DisasContext *s, arg_LDREX *a)
if (!ENABLE_ARCH_8) {
return false;
}
/* We UNDEF for these UNPREDICTABLE cases. */
if (a->rt & 1) {
unallocated_encoding(s);
return true;
@ -9157,8 +9188,13 @@ static bool op_lda(DisasContext *s, arg_LDA *a, MemOp mop)
if (!ENABLE_ARCH_8) {
return false;
}
addr = load_reg(s, a->rn);
/* We UNDEF for these UNPREDICTABLE cases. */
if (a->rn == 15 || a->rt == 15) {
unallocated_encoding(s);
return true;
}
addr = load_reg(s, a->rn);
tmp = tcg_temp_new_i32();
gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data);
disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel);