ppc/xive: introduce a simplified XIVE presenter
The last sub-engine of the XIVE architecture is the Interrupt Virtualization Presentation Engine (IVPE). On HW, the IVRE and the IVPE share elements, the Power Bus interface (CQ), the routing table descriptors, and they can be combined in the same HW logic. We do the same in QEMU and combine both engines in the XiveRouter for simplicity. When the IVRE has completed its job of matching an event source with a Notification Virtual Target (NVT) to notify, it forwards the event notification to the IVPE sub-engine. The IVPE scans the thread interrupt contexts of the Notification Virtual Targets (NVT) dispatched on the HW processor threads and if a match is found, it signals the thread. If not, the IVPE escalates the notification to some other targets and records the notification in a backlog queue. The IVPE maintains the thread interrupt context state for each of its NVTs not dispatched on HW processor threads in the Notification Virtual Target table (NVTT). The model currently only supports single NVT notifications. Signed-off-by: Cédric Le Goater <clg@kaod.org> [dwg: Folded in fix for field accessors] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater
David Gibson
parent
207d9fe985
commit
af53dbf622
190
hw/intc/xive.c
190
hw/intc/xive.c
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@ -984,6 +984,188 @@ int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
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return xrc->write_end(xrtr, end_blk, end_idx, end, word_number);
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}
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int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
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XiveNVT *nvt)
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{
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XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
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return xrc->get_nvt(xrtr, nvt_blk, nvt_idx, nvt);
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}
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int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
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XiveNVT *nvt, uint8_t word_number)
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{
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XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
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return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number);
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}
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/*
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* The thread context register words are in big-endian format.
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*/
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static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format,
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uint8_t nvt_blk, uint32_t nvt_idx,
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bool cam_ignore, uint32_t logic_serv)
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{
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uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx);
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uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]);
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uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
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uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]);
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/*
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* TODO (PowerNV): ignore mode. The low order bits of the NVT
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* identifier are ignored in the "CAM" match.
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*/
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if (format == 0) {
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if (cam_ignore == true) {
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/*
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* F=0 & i=1: Logical server notification (bits ignored at
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* the end of the NVT identifier)
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*/
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qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n",
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nvt_blk, nvt_idx);
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return -1;
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}
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/* F=0 & i=0: Specific NVT notification */
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/* TODO (PowerNV) : PHYS ring */
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/* HV POOL ring */
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if ((be32_to_cpu(qw2w2) & TM_QW2W2_VP) &&
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cam == xive_get_field32(TM_QW2W2_POOL_CAM, qw2w2)) {
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return TM_QW2_HV_POOL;
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}
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/* OS ring */
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if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) &&
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cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) {
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return TM_QW1_OS;
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}
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} else {
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/* F=1 : User level Event-Based Branch (EBB) notification */
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/* USER ring */
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if ((be32_to_cpu(qw1w2) & TM_QW1W2_VO) &&
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(cam == xive_get_field32(TM_QW1W2_OS_CAM, qw1w2)) &&
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(be32_to_cpu(qw0w2) & TM_QW0W2_VU) &&
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(logic_serv == xive_get_field32(TM_QW0W2_LOGIC_SERV, qw0w2))) {
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return TM_QW0_USER;
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}
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}
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return -1;
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}
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typedef struct XiveTCTXMatch {
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XiveTCTX *tctx;
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uint8_t ring;
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} XiveTCTXMatch;
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static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
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uint8_t nvt_blk, uint32_t nvt_idx,
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bool cam_ignore, uint8_t priority,
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uint32_t logic_serv, XiveTCTXMatch *match)
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{
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CPUState *cs;
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/*
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* TODO (PowerNV): handle chip_id overwrite of block field for
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* hardwired CAM compares
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*/
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CPU_FOREACH(cs) {
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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XiveTCTX *tctx = XIVE_TCTX(cpu->intc);
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int ring;
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/*
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* HW checks that the CPU is enabled in the Physical Thread
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* Enable Register (PTER).
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*/
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/*
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* Check the thread context CAM lines and record matches. We
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* will handle CPU exception delivery later
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*/
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ring = xive_presenter_tctx_match(tctx, format, nvt_blk, nvt_idx,
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cam_ignore, logic_serv);
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/*
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* Save the context and follow on to catch duplicates, that we
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* don't support yet.
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*/
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if (ring != -1) {
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if (match->tctx) {
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qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thread "
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"context NVT %x/%x\n", nvt_blk, nvt_idx);
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return false;
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}
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match->ring = ring;
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match->tctx = tctx;
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}
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}
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if (!match->tctx) {
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qemu_log_mask(LOG_UNIMP, "XIVE: NVT %x/%x is not dispatched\n",
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nvt_blk, nvt_idx);
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return false;
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}
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return true;
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}
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/*
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* This is our simple Xive Presenter Engine model. It is merged in the
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* Router as it does not require an extra object.
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*
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* It receives notification requests sent by the IVRE to find one
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* matching NVT (or more) dispatched on the processor threads. In case
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* of a single NVT notification, the process is abreviated and the
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* thread is signaled if a match is found. In case of a logical server
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* notification (bits ignored at the end of the NVT identifier), the
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* IVPE and IVRE select a winning thread using different filters. This
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* involves 2 or 3 exchanges on the PowerBus that the model does not
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* support.
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*
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* The parameters represent what is sent on the PowerBus
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*/
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static void xive_presenter_notify(XiveRouter *xrtr, uint8_t format,
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uint8_t nvt_blk, uint32_t nvt_idx,
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bool cam_ignore, uint8_t priority,
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uint32_t logic_serv)
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{
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XiveNVT nvt;
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XiveTCTXMatch match = { .tctx = NULL, .ring = 0 };
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bool found;
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/* NVT cache lookup */
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if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) {
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qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVT %x/%x\n",
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nvt_blk, nvt_idx);
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return;
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}
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if (!xive_nvt_is_valid(&nvt)) {
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qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is invalid\n",
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nvt_blk, nvt_idx);
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return;
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}
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found = xive_presenter_match(xrtr, format, nvt_blk, nvt_idx, cam_ignore,
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priority, logic_serv, &match);
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if (found) {
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return;
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}
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/*
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* If no matching NVT is dispatched on a HW thread :
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* - update the NVT structure if backlog is activated
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* - escalate (ESe PQ bits and EAS in w4-5) if escalation is
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* activated
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*/
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}
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/*
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* An END trigger can come from an event trigger (IPI or HW) or from
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* another chip. We don't model the PowerBus but the END trigger
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@ -1053,6 +1235,14 @@ static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk,
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/*
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* Follows IVPE notification
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*/
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xive_presenter_notify(xrtr, format,
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xive_get_field32(END_W6_NVT_BLOCK, end.w6),
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xive_get_field32(END_W6_NVT_INDEX, end.w6),
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xive_get_field32(END_W7_F0_IGNORE, end.w7),
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priority,
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xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7));
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/* TODO: Auto EOI. */
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}
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static void xive_router_notify(XiveNotifier *xn, uint32_t lisn)
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@ -325,6 +325,10 @@ typedef struct XiveRouterClass {
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XiveEND *end);
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int (*write_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
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XiveEND *end, uint8_t word_number);
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int (*get_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
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XiveNVT *nvt);
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int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
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XiveNVT *nvt, uint8_t word_number);
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} XiveRouterClass;
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void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon);
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@ -335,6 +339,11 @@ int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
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XiveEND *end);
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int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
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XiveEND *end, uint8_t word_number);
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int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
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XiveNVT *nvt);
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int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
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XiveNVT *nvt, uint8_t word_number);
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/*
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* XIVE END ESBs
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@ -411,4 +420,9 @@ extern const MemoryRegionOps xive_tm_ops;
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void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);
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static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx)
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{
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return (nvt_blk << 19) | nvt_idx;
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}
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#endif /* PPC_XIVE_H */
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@ -208,4 +208,28 @@ typedef struct XiveEND {
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#define xive_end_is_backlog(end) (be32_to_cpu((end)->w0) & END_W0_BACKLOG)
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#define xive_end_is_escalate(end) (be32_to_cpu((end)->w0) & END_W0_ESCALATE_CTL)
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/* Notification Virtual Target (NVT) */
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typedef struct XiveNVT {
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uint32_t w0;
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#define NVT_W0_VALID PPC_BIT32(0)
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uint32_t w1;
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uint32_t w2;
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uint32_t w3;
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uint32_t w4;
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uint32_t w5;
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uint32_t w6;
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uint32_t w7;
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uint32_t w8;
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#define NVT_W8_GRP_VALID PPC_BIT32(0)
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uint32_t w9;
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uint32_t wa;
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uint32_t wb;
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uint32_t wc;
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uint32_t wd;
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uint32_t we;
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uint32_t wf;
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} XiveNVT;
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#define xive_nvt_is_valid(nvt) (be32_to_cpu((nvt)->w0) & NVT_W0_VALID)
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#endif /* PPC_XIVE_REGS_H */
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