From afb661eb902f4ad1456d57b31cdd02f0b4aac33f Mon Sep 17 00:00:00 2001 From: Alex Williamson Date: Thu, 14 Mar 2013 16:01:17 -0600 Subject: [PATCH] pci: Q35, Root Ports, and Switches create PCI Express buses Convert q35, ioh3420, xio3130_upstream, and xio3130_downstream to use the new TYPE_PCIE_BUS. Signed-off-by: Alex Williamson Signed-off-by: Michael S. Tsirkin --- hw/ioh3420.c | 2 +- hw/q35.c | 2 +- hw/xio3130_downstream.c | 2 +- hw/xio3130_upstream.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/ioh3420.c b/hw/ioh3420.c index 74d84d4dda..5cff61e095 100644 --- a/hw/ioh3420.c +++ b/hw/ioh3420.c @@ -97,7 +97,7 @@ static int ioh3420_initfn(PCIDevice *d) PCIESlot *s = DO_UPCAST(PCIESlot, port, p); int rc; - rc = pci_bridge_initfn(d, TYPE_PCI_BUS); + rc = pci_bridge_initfn(d, TYPE_PCIE_BUS); if (rc < 0) { return rc; } diff --git a/hw/q35.c b/hw/q35.c index 37592bc088..6ea081aaa3 100644 --- a/hw/q35.c +++ b/hw/q35.c @@ -55,7 +55,7 @@ static int q35_host_init(SysBusDevice *dev) } b = pci_bus_new(&s->host.pci.busdev.qdev, "pcie.0", s->mch.pci_address_space, s->mch.address_space_io, - 0, TYPE_PCI_BUS); + 0, TYPE_PCIE_BUS); s->host.pci.bus = b; qdev_set_parent_bus(DEVICE(&s->mch), BUS(b)); qdev_init_nofail(DEVICE(&s->mch)); diff --git a/hw/xio3130_downstream.c b/hw/xio3130_downstream.c index a76d89bb6f..b868f56ff9 100644 --- a/hw/xio3130_downstream.c +++ b/hw/xio3130_downstream.c @@ -61,7 +61,7 @@ static int xio3130_downstream_initfn(PCIDevice *d) PCIESlot *s = DO_UPCAST(PCIESlot, port, p); int rc; - rc = pci_bridge_initfn(d, TYPE_PCI_BUS); + rc = pci_bridge_initfn(d, TYPE_PCIE_BUS); if (rc < 0) { return rc; } diff --git a/hw/xio3130_upstream.c b/hw/xio3130_upstream.c index d8fd19e196..cd5d97d211 100644 --- a/hw/xio3130_upstream.c +++ b/hw/xio3130_upstream.c @@ -57,7 +57,7 @@ static int xio3130_upstream_initfn(PCIDevice *d) PCIEPort *p = DO_UPCAST(PCIEPort, br, br); int rc; - rc = pci_bridge_initfn(d, TYPE_PCI_BUS); + rc = pci_bridge_initfn(d, TYPE_PCIE_BUS); if (rc < 0) { return rc; }