spapr: Move spapr_cpu_init() to spapr_cpu_core.c
Start consolidating CPU init related routines in spapr_cpu_core.c. As part of this, move spapr_cpu_init() and its dependencies from spapr.c to spapr_cpu_core.c No functionality change in this patch. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [dwg: Rename TIMEBASE_FREQ to SPAPR_TIMEBASE_FREQ, since it's now in a public(ish) header] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -89,8 +89,6 @@
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#define MIN_RMA_SLOF 128UL
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#define MIN_RMA_SLOF 128UL
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#define TIMEBASE_FREQ 512000000ULL
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#define PHANDLE_XICP 0x00001111
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#define PHANDLE_XICP 0x00001111
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#define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
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#define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
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@ -599,7 +597,8 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
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int index = ppc_get_vcpu_dt_id(cpu);
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int index = ppc_get_vcpu_dt_id(cpu);
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uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
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uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
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0xffffffff, 0xffffffff};
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0xffffffff, 0xffffffff};
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uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ;
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uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
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: SPAPR_TIMEBASE_FREQ;
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uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
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uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
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uint32_t page_sizes_prop[64];
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uint32_t page_sizes_prop[64];
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size_t page_sizes_prop_size;
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size_t page_sizes_prop_size;
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@ -1198,26 +1197,6 @@ static void ppc_spapr_reset(void)
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}
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}
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static void spapr_cpu_reset(void *opaque)
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{
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sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
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PowerPCCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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cpu_reset(cs);
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/* All CPUs start halted. CPU0 is unhalted from the machine level
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* reset code and the rest are explicitly started up by the guest
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* using an RTAS call */
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cs->halted = 1;
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env->spr[SPR_HIOR] = 0;
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ppc_hash64_set_external_hpt(cpu, spapr->htab, spapr->htab_shift,
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&error_fatal);
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}
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static void spapr_create_nvram(sPAPRMachineState *spapr)
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static void spapr_create_nvram(sPAPRMachineState *spapr)
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{
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{
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DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
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DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
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@ -1623,31 +1602,6 @@ static void spapr_boot_set(void *opaque, const char *boot_device,
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machine->boot_order = g_strdup(boot_device);
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machine->boot_order = g_strdup(boot_device);
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}
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}
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void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, Error **errp)
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{
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CPUPPCState *env = &cpu->env;
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/* Set time-base frequency to 512 MHz */
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cpu_ppc_tb_init(env, TIMEBASE_FREQ);
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/* Enable PAPR mode in TCG or KVM */
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cpu_ppc_set_papr(cpu);
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if (cpu->max_compat) {
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Error *local_err = NULL;
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ppc_set_compat(cpu, cpu->max_compat, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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}
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xics_cpu_setup(spapr->icp, cpu);
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qemu_register_reset(spapr_cpu_reset, cpu);
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}
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/*
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/*
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* Reset routine for LMB DR devices.
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* Reset routine for LMB DR devices.
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*
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*
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@ -14,6 +14,54 @@
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#include "qapi/error.h"
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#include "qapi/error.h"
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#include <sysemu/cpus.h>
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#include <sysemu/cpus.h>
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#include "target-ppc/kvm_ppc.h"
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#include "target-ppc/kvm_ppc.h"
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#include "hw/ppc/ppc.h"
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#include "target-ppc/mmu-hash64.h"
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#include <sysemu/numa.h>
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static void spapr_cpu_reset(void *opaque)
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{
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sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
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PowerPCCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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cpu_reset(cs);
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/* All CPUs start halted. CPU0 is unhalted from the machine level
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* reset code and the rest are explicitly started up by the guest
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* using an RTAS call */
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cs->halted = 1;
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env->spr[SPR_HIOR] = 0;
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ppc_hash64_set_external_hpt(cpu, spapr->htab, spapr->htab_shift,
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&error_fatal);
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}
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void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, Error **errp)
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{
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CPUPPCState *env = &cpu->env;
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/* Set time-base frequency to 512 MHz */
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cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
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/* Enable PAPR mode in TCG or KVM */
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cpu_ppc_set_papr(cpu);
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if (cpu->max_compat) {
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Error *local_err = NULL;
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ppc_set_compat(cpu, cpu->max_compat, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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}
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xics_cpu_setup(spapr->icp, cpu);
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qemu_register_reset(spapr_cpu_reset, cpu);
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}
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static int spapr_cpu_core_realize_child(Object *child, void *opaque)
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static int spapr_cpu_core_realize_child(Object *child, void *opaque)
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{
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{
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@ -16,6 +16,8 @@ typedef struct sPAPREventLogEntry sPAPREventLogEntry;
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#define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL
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#define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL
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#define SPAPR_ENTRY_POINT 0x100
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#define SPAPR_ENTRY_POINT 0x100
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#define SPAPR_TIMEBASE_FREQ 512000000ULL
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typedef struct sPAPRMachineClass sPAPRMachineClass;
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typedef struct sPAPRMachineClass sPAPRMachineClass;
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typedef struct sPAPRMachineState sPAPRMachineState;
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typedef struct sPAPRMachineState sPAPRMachineState;
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