haraldwolff
/
qemu-patch-raspberry4
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

linux-user/host/mips: Populate host_signal.h 

Split host_signal_pc and host_signal_write out of user-exec.c.

Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
staging
Richard Henderson 2021-09-17 10:50:14 -07:00
parent 66ee11d407
commit b12161120a
2 changed files with 63 additions and 52 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

52
accel/tcg/user-exec.c
View File

@ -253,57 +253,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
return size ? g2h(env_cpu(env), addr) : NULL;
}
#if defined(__mips__)
#if defined(__misp16) || defined(__mips_micromips)
#error "Unsupported encoding"
#endif
int cpu_signal_handler(int host_signum, void *pinfo,
void *puc)
{
siginfo_t *info = pinfo;
ucontext_t *uc = puc;
uintptr_t pc = uc->uc_mcontext.pc;
uint32_t insn = *(uint32_t *)pc;
int is_write = 0;
/* Detect all store instructions at program counter. */
switch((insn >> 26) & 077) {
case 050: /* SB */
case 051: /* SH */
case 052: /* SWL */
case 053: /* SW */
case 054: /* SDL */
case 055: /* SDR */
case 056: /* SWR */
case 070: /* SC */
case 071: /* SWC1 */
case 074: /* SCD */
case 075: /* SDC1 */
case 077: /* SD */
#if !defined(__mips_isa_rev) || __mips_isa_rev < 6
case 072: /* SWC2 */
case 076: /* SDC2 */
#endif
is_write = 1;
break;
case 023: /* COP1X */
/* Required in all versions of MIPS64 since
MIPS64r1 and subsequent versions of MIPS32r2. */
switch (insn & 077) {
case 010: /* SWXC1 */
case 011: /* SDXC1 */
case 015: /* SUXC1 */
is_write = 1;
}
break;
}
return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
}
#elif defined(__riscv)
#if defined(__riscv)
int cpu_signal_handler(int host_signum, void *pinfo,
void *puc)

63
linux-user/host/mips/host-signal.h
View File

@ -1 +1,62 @@
#define HOST_SIGNAL_PLACEHOLDER
/*
* host-signal.h: signal info dependent on the host architecture
*
* Copyright (c) 2003-2005 Fabrice Bellard
* Copyright (c) 2021 Linaro Limited
*
* This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef MIPS_HOST_SIGNAL_H
#define MIPS_HOST_SIGNAL_H
static inline uintptr_t host_signal_pc(ucontext_t *uc)
{
return uc->uc_mcontext.pc;
}
#if defined(__misp16) || defined(__mips_micromips)
#error "Unsupported encoding"
#endif
static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
{
uint32_t insn = *(uint32_t *)host_signal_pc(uc);
/* Detect all store instructions at program counter. */
switch ((insn >> 26) & 077) {
case 050: /* SB */
case 051: /* SH */
case 052: /* SWL */
case 053: /* SW */
case 054: /* SDL */
case 055: /* SDR */
case 056: /* SWR */
case 070: /* SC */
case 071: /* SWC1 */
case 074: /* SCD */
case 075: /* SDC1 */
case 077: /* SD */
#if !defined(__mips_isa_rev) || __mips_isa_rev < 6
case 072: /* SWC2 */
case 076: /* SDC2 */
#endif
return true;
case 023: /* COP1X */
/*
* Required in all versions of MIPS64 since
* MIPS64r1 and subsequent versions of MIPS32r2.
*/
switch (insn & 077) {
case 010: /* SWXC1 */
case 011: /* SDXC1 */
case 015: /* SUXC1 */
return true;
}
break;
}
return false;
}
#endif