hw/net/pcnet-pci: Unify pcnet_ioport_read/write and pcnet_mmio_read/write
The only difference between our implementation of the pcnet ioport
accessors and the mmio accessors is that the former check BCR_DWIO to
see what access widths are permitted for addresses in the aprom range
(0x0..0xf). In fact our failure to do this in the mmio accessors
is a bug (one which was fixed for the ioport accessors in
commit 7ba7974197
in 2011).
The data sheet for the Am79C970A does not describe the DWIO
bit as only applying for I/O space mapped I/O resources and
not memory mapped I/O resources, and our MMIO accessors already
honour DWIO for accesses in the 0x10..0x1f range (since the
pcnet_ioport_{read,write}{w,l} functions check it).
The data sheet for the later but compatible Am79C976 is clearer:
it states specifically "DWIO mode applies to both I/O- and
memory-mapped acceses." This seems to be reasonable evidence
in favour of interpretating the Am79C970A spec as being the same.
(NB: Linux's pcnet driver only supports I/O accesses, so the
MMIO access part of this device is probably untested anyway.)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
parent
5d026de8b6
commit
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@ -139,69 +139,6 @@ static const MemoryRegionOps pcnet_io_ops = {
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.endianness = DEVICE_LITTLE_ENDIAN,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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};
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/*
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* TODO: should MMIO accesses to the addresses corresponding to the
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* APROM also honour the BCR_DWIO() setting? If so, then these functions
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* and pcnet_ioport_write/pcnet_ioport_read could be merged.
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* If not, then should pcnet_ioport_{read,write}{w,l} really check
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* BCR_DWIO() for MMIO writes ?
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*/
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static void pcnet_mmio_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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PCNetState *d = opaque;
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trace_pcnet_mmio_write(opaque, addr, size, val);
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if (addr < 0x10) {
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if (size == 1) {
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pcnet_aprom_writeb(d, addr, data);
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} else if ((addr & 1) == 0 && size == 2) {
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pcnet_aprom_writeb(d, addr, data & 0xff);
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pcnet_aprom_writeb(d, addr + 1, data >> 8);
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} else if ((addr & 3) == 0 && size == 4) {
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pcnet_aprom_writeb(d, addr, data & 0xff);
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pcnet_aprom_writeb(d, addr + 1, (data >> 8) & 0xff);
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pcnet_aprom_writeb(d, addr + 2, (data >> 16) & 0xff);
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pcnet_aprom_writeb(d, addr + 3, data >> 24);
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}
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} else {
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if (size == 2) {
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pcnet_ioport_writew(d, addr, data);
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} else if (size == 4) {
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pcnet_ioport_writel(d, addr, data);
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}
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}
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}
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static uint64_t pcnet_mmio_read(void *opque, hwaddr addr, unsigned size)
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{
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PCNetState *d = opaque;
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trace_pcnet_ioport_read(opaque, addr, size);
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if (addr < 0x10) {
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if (size == 1) {
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return pcnet_aprom_readb(d, addr);
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} else if ((addr & 1) == 0 && size == 2) {
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return pcnet_aprom_readb(d, addr) |
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(pcnet_aprom_readb(d, addr + 1) << 8);
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} else if ((addr & 3) == 0 && size == 4) {
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return pcnet_aprom_readb(d, addr) |
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(pcnet_aprom_readb(d, addr + 1) << 8) |
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(pcnet_aprom_readb(d, addr + 2) << 16) |
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(pcnet_aprom_readb(d, addr + 3) << 24);
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}
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} else {
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if (size == 2) {
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return pcnet_ioport_readw(d, addr);
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} else if (size == 4) {
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return pcnet_ioport_readl(d, addr);
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}
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}
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return ((uint64_t)1 << (size * 8)) - 1;
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}
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static const VMStateDescription vmstate_pci_pcnet = {
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static const VMStateDescription vmstate_pci_pcnet = {
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.name = "pcnet",
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.name = "pcnet",
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.version_id = 3,
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.version_id = 3,
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@ -216,8 +153,8 @@ static const VMStateDescription vmstate_pci_pcnet = {
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/* PCI interface */
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/* PCI interface */
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static const MemoryRegionOps pcnet_mmio_ops = {
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static const MemoryRegionOps pcnet_mmio_ops = {
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.read = pcnet_mmio_read,
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.read = pcnet_ioport_read,
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.write = pcnet_mmio_write,
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.write = pcnet_ioport_write,
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.valid.min_access_size = 1,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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.valid.max_access_size = 4,
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.impl.min_access_size = 1,
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.impl.min_access_size = 1,
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@ -61,8 +61,6 @@ pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val) "opaque=%p addr=0x
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pcnet_aprom_readb(void *opaque, uint32_t addr, uint32_t val) "opaque=%p addr=0x%08x val=0x%02x"
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pcnet_aprom_readb(void *opaque, uint32_t addr, uint32_t val) "opaque=%p addr=0x%08x val=0x%02x"
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pcnet_ioport_read(void *opaque, uint64_t addr, unsigned size) "opaque=%p addr=0x%"PRIx64" size=%d"
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pcnet_ioport_read(void *opaque, uint64_t addr, unsigned size) "opaque=%p addr=0x%"PRIx64" size=%d"
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pcnet_ioport_write(void *opaque, uint64_t addr, uint64_t data, unsigned size) "opaque=%p addr=0x%"PRIx64" data=0x%"PRIx64" size=%d"
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pcnet_ioport_write(void *opaque, uint64_t addr, uint64_t data, unsigned size) "opaque=%p addr=0x%"PRIx64" data=0x%"PRIx64" size=%d"
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pcnet_mmio_write(void *opaque, uint64_t addr, uint32_t val, unsigned size) "opaque=%p addr=0x%"PRIx64" val=0x%x size=%d"
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pcnet_mmio_read(void *opaque, uint64_t addr, unsigned size) "opaque=%p addr=0x%"PRIx64" size=%d"
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# hw/net/net_rx_pkt.c
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# hw/net/net_rx_pkt.c
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net_rx_pkt_parsed(bool ip4, bool ip6, bool udp, bool tcp, size_t l3o, size_t l4o, size_t l5o) "RX packet parsed: ip4: %d, ip6: %d, udp: %d, tcp: %d, l3 offset: %zu, l4 offset: %zu, l5 offset: %zu"
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net_rx_pkt_parsed(bool ip4, bool ip6, bool udp, bool tcp, size_t l3o, size_t l4o, size_t l5o) "RX packet parsed: ip4: %d, ip6: %d, udp: %d, tcp: %d, l3 offset: %zu, l4 offset: %zu, l5 offset: %zu"
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