apb: fix endianness for APB and PCI config accesses
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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@ -559,7 +559,7 @@ static uint64_t apb_config_readl (void *opaque,
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static const MemoryRegionOps apb_config_ops = {
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static const MemoryRegionOps apb_config_ops = {
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.read = apb_config_readl,
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.read = apb_config_readl,
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.write = apb_config_writel,
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.write = apb_config_writel,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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};
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static void apb_pci_config_write(void *opaque, hwaddr addr,
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static void apb_pci_config_write(void *opaque, hwaddr addr,
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@ -568,7 +568,6 @@ static void apb_pci_config_write(void *opaque, hwaddr addr,
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APBState *s = opaque;
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APBState *s = opaque;
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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val = qemu_bswap_len(val, size);
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APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
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APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
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pci_data_write(phb->bus, addr, val, size);
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pci_data_write(phb->bus, addr, val, size);
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}
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}
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@ -581,7 +580,6 @@ static uint64_t apb_pci_config_read(void *opaque, hwaddr addr,
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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ret = pci_data_read(phb->bus, addr, size);
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ret = pci_data_read(phb->bus, addr, size);
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ret = qemu_bswap_len(ret, size);
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APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret);
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APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret);
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return ret;
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return ret;
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}
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}
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@ -743,7 +741,7 @@ static void pci_pbm_reset(DeviceState *d)
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static const MemoryRegionOps pci_config_ops = {
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static const MemoryRegionOps pci_config_ops = {
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.read = apb_pci_config_read,
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.read = apb_pci_config_read,
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.write = apb_pci_config_write,
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.write = apb_pci_config_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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};
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static int pci_pbm_init_device(SysBusDevice *dev)
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static int pci_pbm_init_device(SysBusDevice *dev)
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