PL080 qdev conversion
Signed-off-by: Paul Brook <paul@codesourcery.com>
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82634c2d74
commit
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36
hw/pl080.c
36
hw/pl080.c
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@ -7,8 +7,7 @@
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* This code is licenced under the GPL.
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* This code is licenced under the GPL.
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*/
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*/
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#include "hw.h"
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#include "sysbus.h"
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#include "primecell.h"
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#define PL080_MAX_CHANNELS 8
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#define PL080_MAX_CHANNELS 8
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#define PL080_CONF_E 0x1
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#define PL080_CONF_E 0x1
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@ -37,6 +36,7 @@ typedef struct {
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} pl080_channel;
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} pl080_channel;
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typedef struct {
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typedef struct {
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SysBusDevice busdev;
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uint8_t tc_int;
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uint8_t tc_int;
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uint8_t tc_mask;
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uint8_t tc_mask;
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uint8_t err_int;
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uint8_t err_int;
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@ -319,19 +319,35 @@ static CPUWriteMemoryFunc *pl080_writefn[] = {
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pl080_write
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pl080_write
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};
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};
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/* The PL080 and PL081 are the same except for the number of channels
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static void pl08x_init(SysBusDevice *dev, int nchannels)
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they implement (8 and 2 respectively). */
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void *pl080_init(uint32_t base, qemu_irq irq, int nchannels)
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{
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{
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int iomemtype;
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int iomemtype;
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pl080_state *s;
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pl080_state *s = FROM_SYSBUS(pl080_state, dev);
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s = (pl080_state *)qemu_mallocz(sizeof(pl080_state));
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iomemtype = cpu_register_io_memory(0, pl080_readfn,
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iomemtype = cpu_register_io_memory(0, pl080_readfn,
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pl080_writefn, s);
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pl080_writefn, s);
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cpu_register_physical_memory(base, 0x00001000, iomemtype);
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sysbus_init_mmio(dev, 0x1000, iomemtype);
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s->irq = irq;
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sysbus_init_irq(dev, &s->irq);
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s->nchannels = nchannels;
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s->nchannels = nchannels;
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/* ??? Save/restore. */
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/* ??? Save/restore. */
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return s;
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}
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}
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static void pl080_init(SysBusDevice *dev)
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{
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pl08x_init(dev, 8);
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}
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static void pl081_init(SysBusDevice *dev)
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{
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pl08x_init(dev, 2);
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}
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/* The PL080 and PL081 are the same except for the number of channels
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they implement (8 and 2 respectively). */
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static void pl080_register_devices(void)
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{
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sysbus_register_dev("pl080", sizeof(pl080_state), pl080_init);
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sysbus_register_dev("pl081", sizeof(pl080_state), pl081_init);
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}
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device_init(pl080_register_devices)
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@ -89,7 +89,7 @@ static void realview_init(ram_addr_t ram_size,
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sysbus_create_simple("pl011", 0x1000c000, pic[15]);
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sysbus_create_simple("pl011", 0x1000c000, pic[15]);
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/* DMA controller is optional, apparently. */
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/* DMA controller is optional, apparently. */
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pl080_init(0x10030000, pic[24], 2);
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sysbus_create_simple("pl081", 0x10030000, pic[24]);
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sysbus_create_simple("sp804", 0x10011000, pic[4]);
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sysbus_create_simple("sp804", 0x10011000, pic[4]);
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sysbus_create_simple("sp804", 0x10012000, pic[5]);
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sysbus_create_simple("sp804", 0x10012000, pic[5]);
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@ -226,7 +226,7 @@ static void versatile_init(ram_addr_t ram_size,
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sysbus_create_simple("pl011", 0x101f3000, pic[14]);
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sysbus_create_simple("pl011", 0x101f3000, pic[14]);
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sysbus_create_simple("pl011", 0x10009000, sic[6]);
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sysbus_create_simple("pl011", 0x10009000, sic[6]);
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pl080_init(0x10130000, pic[17], 8);
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sysbus_create_simple("pl080", 0x10130000, pic[17]);
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sysbus_create_simple("sp804", 0x101e2000, pic[4]);
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sysbus_create_simple("sp804", 0x101e2000, pic[4]);
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sysbus_create_simple("sp804", 0x101e3000, pic[5]);
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sysbus_create_simple("sp804", 0x101e3000, pic[5]);
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