Fix configuration 2 register (esp_2_cfg2.diff):
According to http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt, "Any bit pattern written to this register may be read back and should be identical" Signed-off-by: Herve Poussineau <hpoussin@reactos.org> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5812 c046a42c-6fe2-441c-8c8c-71466251a162
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8dea1dd406
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7
hw/esp.c
7
hw/esp.c
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@ -144,8 +144,6 @@ struct ESPState {
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#define CFG1_RESREPT 0x40
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#define CFG1_RESREPT 0x40
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#define CFG2_MASK 0x15
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#define TCHI_FAS100A 0x4
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#define TCHI_FAS100A 0x4
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static void esp_raise_irq(ESPState *s)
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static void esp_raise_irq(ESPState *s)
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@ -552,10 +550,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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break;
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break;
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case ESP_WCCF ... ESP_WTEST:
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case ESP_WCCF ... ESP_WTEST:
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break;
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break;
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case ESP_CFG2:
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case ESP_CFG2 ... ESP_RES4:
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s->rregs[saddr] = val & CFG2_MASK;
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break;
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case ESP_CFG3 ... ESP_RES4:
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s->rregs[saddr] = val;
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s->rregs[saddr] = val;
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break;
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break;
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default:
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default:
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