target-mips: add support for CP0_Config5
Add CP0_Config5, define rw_bitmask and enable modifications. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
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@ -73,6 +73,7 @@ struct CPUMIPSFPUContext {
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float_status fp_status;
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float_status fp_status;
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/* fpu implementation/revision register (fir) */
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/* fpu implementation/revision register (fir) */
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uint32_t fcr0;
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uint32_t fcr0;
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#define FCR0_UFRP 28
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#define FCR0_F64 22
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#define FCR0_F64 22
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#define FCR0_L 21
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#define FCR0_L 21
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#define FCR0_W 20
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#define FCR0_W 20
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@ -371,6 +372,15 @@ struct CPUMIPSState {
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uint32_t CP0_Config4;
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uint32_t CP0_Config4;
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uint32_t CP0_Config4_rw_bitmask;
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uint32_t CP0_Config4_rw_bitmask;
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#define CP0C4_M 31
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#define CP0C4_M 31
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uint32_t CP0_Config5;
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uint32_t CP0_Config5_rw_bitmask;
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#define CP0C5_M 31
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#define CP0C5_K 30
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#define CP0C5_CV 29
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#define CP0C5_EVA 28
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#define CP0C5_MSAEn 27
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#define CP0C5_UFR 2
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#define CP0C5_NFExists 0
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int32_t CP0_Config6;
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int32_t CP0_Config6;
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int32_t CP0_Config7;
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int32_t CP0_Config7;
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/* XXX: Maybe make LLAddr per-TC? */
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/* XXX: Maybe make LLAddr per-TC? */
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@ -135,6 +135,7 @@ DEF_HELPER_2(mttc0_ebase, void, env, tl)
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DEF_HELPER_2(mtc0_config0, void, env, tl)
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DEF_HELPER_2(mtc0_config0, void, env, tl)
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DEF_HELPER_2(mtc0_config2, void, env, tl)
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DEF_HELPER_2(mtc0_config2, void, env, tl)
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DEF_HELPER_2(mtc0_config4, void, env, tl)
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DEF_HELPER_2(mtc0_config4, void, env, tl)
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DEF_HELPER_2(mtc0_config5, void, env, tl)
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DEF_HELPER_2(mtc0_lladdr, void, env, tl)
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DEF_HELPER_2(mtc0_lladdr, void, env, tl)
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DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32)
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DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32)
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DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32)
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DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32)
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@ -1495,6 +1495,12 @@ void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
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(arg1 & env->CP0_Config4_rw_bitmask);
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(arg1 & env->CP0_Config4_rw_bitmask);
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}
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}
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void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
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{
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env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
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(arg1 & env->CP0_Config5_rw_bitmask);
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}
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void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
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void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
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{
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{
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target_long mask = env->CP0_LLAddr_rw_bitmask;
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target_long mask = env->CP0_LLAddr_rw_bitmask;
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@ -4409,7 +4409,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
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rn = "Config4";
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rn = "Config4";
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break;
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break;
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/* 5 is reserved */
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case 5:
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
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rn = "Config5";
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break;
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/* 6,7 are implementation dependent */
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/* 6,7 are implementation dependent */
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case 6:
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case 6:
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
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@ -4991,7 +4994,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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rn = "Config4";
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rn = "Config4";
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ctx->bstate = BS_STOP;
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ctx->bstate = BS_STOP;
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break;
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break;
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/* 5 is reserved */
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case 5:
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gen_helper_mtc0_config5(cpu_env, arg);
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rn = "Config5";
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/* Stop translation as we may have switched the execution mode */
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ctx->bstate = BS_STOP;
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break;
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/* 6,7 are implementation dependent */
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/* 6,7 are implementation dependent */
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case 6:
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case 6:
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/* ignored */
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/* ignored */
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@ -15927,6 +15935,8 @@ void cpu_state_reset(CPUMIPSState *env)
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env->CP0_Config3 = env->cpu_model->CP0_Config3;
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env->CP0_Config3 = env->cpu_model->CP0_Config3;
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env->CP0_Config4 = env->cpu_model->CP0_Config4;
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env->CP0_Config4 = env->cpu_model->CP0_Config4;
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env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask;
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env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask;
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env->CP0_Config5 = env->cpu_model->CP0_Config5;
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env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask;
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env->CP0_Config6 = env->cpu_model->CP0_Config6;
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env->CP0_Config6 = env->cpu_model->CP0_Config6;
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env->CP0_Config7 = env->cpu_model->CP0_Config7;
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env->CP0_Config7 = env->cpu_model->CP0_Config7;
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env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
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env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
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@ -48,6 +48,9 @@
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#define MIPS_CONFIG4 \
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#define MIPS_CONFIG4 \
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((0 << CP0C4_M))
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((0 << CP0C4_M))
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#define MIPS_CONFIG5 \
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((0 << CP0C5_M))
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/* MMU types, the first four entries have the same layout as the
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/* MMU types, the first four entries have the same layout as the
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CP0C0_MT field. */
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CP0C0_MT field. */
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enum mips_mmu_types {
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enum mips_mmu_types {
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@ -69,6 +72,8 @@ struct mips_def_t {
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int32_t CP0_Config3;
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int32_t CP0_Config3;
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int32_t CP0_Config4;
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int32_t CP0_Config4;
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int32_t CP0_Config4_rw_bitmask;
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int32_t CP0_Config4_rw_bitmask;
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int32_t CP0_Config5;
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int32_t CP0_Config5_rw_bitmask;
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int32_t CP0_Config6;
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int32_t CP0_Config6;
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int32_t CP0_Config7;
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int32_t CP0_Config7;
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target_ulong CP0_LLAddr_rw_bitmask;
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target_ulong CP0_LLAddr_rw_bitmask;
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@ -351,8 +356,13 @@ static const mips_def_t mips_defs[] =
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(1 << CP0C1_CA),
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(1 << CP0C1_CA),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_M),
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.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_M),
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.CP0_Config4 = MIPS_CONFIG4,
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.CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M),
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.CP0_Config4_rw_bitmask = 0,
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.CP0_Config4_rw_bitmask = 0,
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.CP0_Config5 = MIPS_CONFIG5,
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.CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) |
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(1 << CP0C5_CV) | (0 << CP0C5_EVA) |
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(1 << CP0C5_MSAEn) | (0 << CP0C5_UFR) |
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(0 << CP0C5_NFExists),
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.CP0_LLAddr_rw_bitmask = 0,
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.CP0_LLAddr_rw_bitmask = 0,
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.CP0_LLAddr_shift = 4,
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.CP0_LLAddr_shift = 4,
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.SYNCI_Step = 32,
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.SYNCI_Step = 32,
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