target-ppc: Remove POWER7+ and POWER8E families
POWER8E is architecturally equal to POWER8 and POWER7+ is equal to POWER7. Also no user space tool makes any difference for CPU node name in the device tree (such as PowerPC,POWER7@0 vs. PowerPC,POWER7+@0). So there is no point in emulating POWER7+ and POWER8E apart from POWER7 and POWER8. Also, the previos patch implemented multiple PVR mask support per CPU class so POWER7 class now covers both POWER7 and POWER7+ CPUs, same is valid for POWER8/8E. This removes POWER7+ and POWER8E classes. This replaces references to POWER7P/POWER8E families with POWER7/POWER8 families. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
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@ -1135,9 +1135,9 @@
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#endif
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#endif
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POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POWER7,
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POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POWER7,
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"POWER7 v2.3")
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"POWER7 v2.3")
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POWERPC_DEF("POWER7+_v2.1", CPU_POWERPC_POWER7P_v21, POWER7P,
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POWERPC_DEF("POWER7+_v2.1", CPU_POWERPC_POWER7P_v21, POWER7,
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"POWER7+ v2.1")
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"POWER7+ v2.1")
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POWERPC_DEF("POWER8E_v1.0", CPU_POWERPC_POWER8E_v10, POWER8E,
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POWERPC_DEF("POWER8E_v1.0", CPU_POWERPC_POWER8E_v10, POWER8,
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"POWER8E v1.0")
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"POWER8E v1.0")
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POWERPC_DEF("POWER8_v1.0", CPU_POWERPC_POWER8_v10, POWER8,
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POWERPC_DEF("POWER8_v1.0", CPU_POWERPC_POWER8_v10, POWER8,
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"POWER8 v1.0")
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"POWER8 v1.0")
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@ -8133,66 +8133,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
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pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
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pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
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}
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}
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POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
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dc->fw_name = "PowerPC,POWER7+";
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dc->desc = "POWER7+";
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dc->props = powerpc_servercpu_properties;
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pcc->pvr_match = ppc_pvr_match_power7;
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pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06;
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pcc->init_proc = init_proc_POWER7;
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pcc->check_pow = check_pow_nocheck;
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pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
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PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
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PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
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PPC_FLOAT_FRSQRTES |
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PPC_FLOAT_STFIWX |
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PPC_FLOAT_EXT |
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PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
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PPC_MEM_SYNC | PPC_MEM_EIEIO |
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PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
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PPC_64B | PPC_ALTIVEC |
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PPC_SEGMENT_64B | PPC_SLBI |
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PPC_POPCNTB | PPC_POPCNTWD;
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pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
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PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
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PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
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PPC2_FP_TST_ISA206;
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pcc->msr_mask = (1ull << MSR_SF) |
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(1ull << MSR_VR) |
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(1ull << MSR_VSX) |
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(1ull << MSR_EE) |
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(1ull << MSR_PR) |
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(1ull << MSR_FP) |
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(1ull << MSR_ME) |
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(1ull << MSR_FE0) |
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(1ull << MSR_SE) |
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(1ull << MSR_DE) |
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(1ull << MSR_FE1) |
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(1ull << MSR_IR) |
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(1ull << MSR_DR) |
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(1ull << MSR_PMM) |
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(1ull << MSR_RI) |
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(1ull << MSR_LE);
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pcc->mmu_model = POWERPC_MMU_2_06;
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#if defined(CONFIG_SOFTMMU)
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pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
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#endif
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pcc->excp_model = POWERPC_EXCP_POWER7;
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pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
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pcc->bfd_mach = bfd_mach_ppc64;
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pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
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POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
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POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
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POWERPC_FLAG_VSX;
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pcc->l1_dcache_size = 0x8000;
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pcc->l1_icache_size = 0x8000;
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pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
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}
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static void init_proc_POWER8(CPUPPCState *env)
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static void init_proc_POWER8(CPUPPCState *env)
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{
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{
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init_proc_book3s_64(env, BOOK3S_CPU_POWER8);
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init_proc_book3s_64(env, BOOK3S_CPU_POWER8);
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@ -8209,13 +8149,13 @@ static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
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return false;
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return false;
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}
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}
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POWERPC_FAMILY(POWER8E)(ObjectClass *oc, void *data)
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POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
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{
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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DeviceClass *dc = DEVICE_CLASS(oc);
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PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
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PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
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dc->fw_name = "PowerPC,POWER8";
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dc->fw_name = "PowerPC,POWER8";
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dc->desc = "POWER8E";
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dc->desc = "POWER8";
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dc->props = powerpc_servercpu_properties;
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dc->props = powerpc_servercpu_properties;
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pcc->pvr_match = ppc_pvr_match_power8;
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pcc->pvr_match = ppc_pvr_match_power8;
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pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06;
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pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06;
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@ -8271,15 +8211,6 @@ POWERPC_FAMILY(POWER8E)(ObjectClass *oc, void *data)
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pcc->l1_icache_size = 0x8000;
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pcc->l1_icache_size = 0x8000;
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pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
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pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
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}
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}
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POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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ppc_POWER8E_cpu_family_class_init(oc, data);
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dc->desc = "POWER8";
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}
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#endif /* defined (TARGET_PPC64) */
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#endif /* defined (TARGET_PPC64) */
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