target/arm: Convert the VCVT-from-f16 insns to decodetree
Convert the VCVTT, VCVTB instructions that deal with conversion from half-precision floats to f32 or 64 to decodetree. Since we're no longer constrained to the old decoder's style using cpu_F0s and cpu_F0d we can perform a direct 16 bit load of the right half of the input single-precision register rather than loading the full 32 bits and then doing a separate shift or sign-extension. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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@ -30,6 +30,26 @@
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#include "decode-vfp.inc.c"
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#include "decode-vfp-uncond.inc.c"
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/*
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* Return the offset of a 16-bit half of the specified VFP single-precision
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* register. If top is true, returns the top 16 bits; otherwise the bottom
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* 16 bits.
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*/
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static inline long vfp_f16_offset(unsigned reg, bool top)
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{
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long offs = vfp_reg_offset(false, reg);
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#ifdef HOST_WORDS_BIGENDIAN
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if (!top) {
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offs += 2;
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}
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#else
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if (top) {
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offs += 2;
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}
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#endif
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return offs;
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}
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/*
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* Check that VFP access is enabled. If it is, do the necessary
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* M-profile lazy-FP handling and then return true.
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@ -2013,3 +2033,65 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
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return true;
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}
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static bool trans_VCVT_f32_f16(DisasContext *s, arg_VCVT_f32_f16 *a)
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{
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TCGv_ptr fpst;
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TCGv_i32 ahp_mode;
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TCGv_i32 tmp;
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if (!dc_isar_feature(aa32_fp16_spconv, s)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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fpst = get_fpstatus_ptr(false);
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ahp_mode = get_ahp_flag();
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tmp = tcg_temp_new_i32();
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/* The T bit tells us if we want the low or high 16 bits of Vm */
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tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t));
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gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp_mode);
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neon_store_reg32(tmp, a->vd);
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tcg_temp_free_i32(ahp_mode);
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tcg_temp_free_ptr(fpst);
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tcg_temp_free_i32(tmp);
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return true;
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}
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static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
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{
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TCGv_ptr fpst;
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TCGv_i32 ahp_mode;
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TCGv_i32 tmp;
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TCGv_i64 vd;
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if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
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return false;
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}
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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fpst = get_fpstatus_ptr(false);
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ahp_mode = get_ahp_flag();
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tmp = tcg_temp_new_i32();
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/* The T bit tells us if we want the low or high 16 bits of Vm */
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tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t));
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vd = tcg_temp_new_i64();
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gen_helper_vfp_fcvt_f16_to_f64(vd, tmp, fpst, ahp_mode);
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neon_store_reg64(vd, a->vd);
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tcg_temp_free_i32(ahp_mode);
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tcg_temp_free_ptr(fpst);
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tcg_temp_free_i32(tmp);
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tcg_temp_free_i64(vd);
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return true;
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}
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@ -3066,7 +3066,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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return 1;
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case 15:
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switch (rn) {
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case 0 ... 3:
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case 0 ... 5:
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case 8 ... 11:
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/* Already handled by decodetree */
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return 1;
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@ -3080,24 +3080,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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if (op == 15) {
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/* rn is opcode, encoded as per VFP_SREG_N. */
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switch (rn) {
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case 0x04: /* vcvtb.f64.f16, vcvtb.f32.f16 */
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case 0x05: /* vcvtt.f64.f16, vcvtt.f32.f16 */
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/*
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* VCVTB, VCVTT: only present with the halfprec extension
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* UNPREDICTABLE if bit 8 is set prior to ARMv8
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* (we choose to UNDEF)
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*/
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if (dp) {
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if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
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return 1;
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}
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} else {
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if (!dc_isar_feature(aa32_fp16_spconv, s)) {
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return 1;
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}
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}
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rm_is_dp = false;
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break;
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case 0x06: /* vcvtb.f16.f32, vcvtb.f16.f64 */
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case 0x07: /* vcvtt.f16.f32, vcvtt.f16.f64 */
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if (dp) {
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@ -3239,42 +3221,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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switch (op) {
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case 15: /* extension space */
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switch (rn) {
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case 4: /* vcvtb.f32.f16, vcvtb.f64.f16 */
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{
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TCGv_ptr fpst = get_fpstatus_ptr(false);
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TCGv_i32 ahp_mode = get_ahp_flag();
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tmp = gen_vfp_mrs();
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tcg_gen_ext16u_i32(tmp, tmp);
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if (dp) {
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gen_helper_vfp_fcvt_f16_to_f64(cpu_F0d, tmp,
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fpst, ahp_mode);
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} else {
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gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp,
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fpst, ahp_mode);
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}
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tcg_temp_free_i32(ahp_mode);
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tcg_temp_free_ptr(fpst);
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tcg_temp_free_i32(tmp);
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break;
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}
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case 5: /* vcvtt.f32.f16, vcvtt.f64.f16 */
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{
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TCGv_ptr fpst = get_fpstatus_ptr(false);
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TCGv_i32 ahp = get_ahp_flag();
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tmp = gen_vfp_mrs();
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tcg_gen_shri_i32(tmp, tmp, 16);
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if (dp) {
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gen_helper_vfp_fcvt_f16_to_f64(cpu_F0d, tmp,
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fpst, ahp);
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} else {
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gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp,
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fpst, ahp);
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}
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tcg_temp_free_i32(tmp);
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tcg_temp_free_i32(ahp);
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tcg_temp_free_ptr(fpst);
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break;
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}
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case 6: /* vcvtb.f16.f32, vcvtb.f16.f64 */
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{
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TCGv_ptr fpst = get_fpstatus_ptr(false);
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@ -181,3 +181,9 @@ VCMP_sp ---- 1110 1.11 010 z:1 .... 1010 e:1 1.0 .... \
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vd=%vd_sp vm=%vm_sp
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VCMP_dp ---- 1110 1.11 010 z:1 .... 1011 e:1 1.0 .... \
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vd=%vd_dp vm=%vm_dp
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# VCVTT and VCVTB from f16: Vd format depends on size bit; Vm is always vm_sp
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VCVT_f32_f16 ---- 1110 1.11 0010 .... 1010 t:1 1.0 .... \
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vd=%vd_sp vm=%vm_sp
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VCVT_f64_f16 ---- 1110 1.11 0010 .... 1011 t:1 1.0 .... \
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vd=%vd_dp vm=%vm_sp
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