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arm: Abstract out "are we singlestepping" test to utility function

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We now test for "are we singlestepping" in several places and
it's not a trivial check because we need to care about both
architectural singlestep and QEMU gdbstub singlestep. We're
also about to add another place that needs to make this check,
so pull the condition out into a function.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1491844419-12485-7-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2017-04-20 17:32:30 +01:00
parent f021b2c462
commit b636649f5a
1 changed files with 15 additions and 5 deletions
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20
target/arm/translate.c
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@ -309,6 +309,17 @@ static void gen_singlestep_exception(DisasContext *s)
}
}
static inline bool is_singlestepping(DisasContext *s)
{
/* Return true if we are singlestepping either because of
* architectural singlestep or QEMU gdbstub singlestep. This does
* not include the command line '-singlestep' mode which is rather
* misnamed as it only means "one instruction per TB" and doesn't
* affect the code we generate.
*/
return s->singlestep_enabled || s->ss_active;
}
static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
{
TCGv_i32 tmp1 = tcg_temp_new_i32();
@ -4104,7 +4115,7 @@ static inline void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
static inline void gen_jmp (DisasContext *s, uint32_t dest)
{
if (unlikely(s->singlestep_enabled || s->ss_active)) {
if (unlikely(is_singlestepping(s))) {
/* An indirect jump so that we still trigger the debug exception. */
if (s->thumb)
dest |= 1;
@ -11970,9 +11981,8 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
((dc->pc >= next_page_start - 3) && insn_crosses_page(env, dc));
} while (!dc->is_jmp && !tcg_op_buf_full() &&
!cs->singlestep_enabled &&
!is_singlestepping(dc) &&
!singlestep &&
!dc->ss_active &&
!end_of_page &&
num_insns < max_insns);
@ -11989,7 +11999,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
instruction was a conditional branch or trap, and the PC has
already been written. */
gen_set_condexec(dc);
if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
if (unlikely(is_singlestepping(dc))) {
/* Unconditional and "condition passed" instruction codepath. */
switch (dc->is_jmp) {
case DISAS_SWI:
@ -12067,7 +12077,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
/* "Condition failed" instruction codepath for the branch/trap insn */
gen_set_label(dc->condlabel);
gen_set_condexec(dc);
if (unlikely(cs->singlestep_enabled || dc->ss_active)) {
if (unlikely(is_singlestepping(dc))) {
gen_set_pc_im(dc, dc->pc);
gen_singlestep_exception(dc);
} else {