RISC-V: No traps on writes to misa,minstret,mcycle
These fields are marked WARL (Write Any Values, Reads Legal Values) in the RISC-V Privileged Architecture Specification so instead of raising exceptions, illegal writes are silently dropped. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com>
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@ -213,17 +213,19 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
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break;
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}
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case CSR_MINSTRET:
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qemu_log_mask(LOG_UNIMP, "CSR_MINSTRET: write not implemented");
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goto do_illegal;
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/* minstret is WARL so unsupported writes are ignored */
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break;
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case CSR_MCYCLE:
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qemu_log_mask(LOG_UNIMP, "CSR_MCYCLE: write not implemented");
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goto do_illegal;
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/* mcycle is WARL so unsupported writes are ignored */
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break;
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#if defined(TARGET_RISCV32)
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case CSR_MINSTRETH:
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qemu_log_mask(LOG_UNIMP, "CSR_MINSTRETH: write not implemented");
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goto do_illegal;
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/* minstreth is WARL so unsupported writes are ignored */
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break;
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case CSR_MCYCLEH:
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qemu_log_mask(LOG_UNIMP, "CSR_MCYCLEH: write not implemented");
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goto do_illegal;
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/* mcycleh is WARL so unsupported writes are ignored */
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break;
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#endif
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case CSR_MUCOUNTEREN:
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if (env->priv_ver <= PRIV_VERSION_1_09_1) {
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env->scounteren = val_to_write;
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@ -337,10 +339,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
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case CSR_MBADADDR:
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env->mbadaddr = val_to_write;
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break;
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case CSR_MISA: {
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qemu_log_mask(LOG_UNIMP, "CSR_MISA: misa writes not supported");
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goto do_illegal;
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}
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case CSR_MISA:
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/* misa is WARL so unsupported writes are ignored */
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break;
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case CSR_PMPCFG0:
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case CSR_PMPCFG1:
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case CSR_PMPCFG2:
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