hw/dispaly/sm501: bugfixes, add sanity checks.
hw/display: use tracepoints, misc cleanups. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABCgAGBQJez7AUAAoJEEy22O7T6HE4JvgQAKtszLGyFKlkFv1RDuUc35NY hWsEbglGPesn2jFMxL1TI7hr+yb7qyaakbsv1WBhRpmI22BXJcNRjGv9XlWDzp7i LnE2Zm5WwJ6Z53G70inybzIp1sRLvZXl8c0218/bCiH1i37OR+dwXGmg8lMhU13P QcVmzPYSVqj8/qkS6zmZHMbkVk2jonOp7S0wqxI7GHgAclB5K4BZHy4i+s0V2zYK KesIvVdyFvgqzIWvR3CwJC7HKVDBz4whDwzASNdICUbEj+C99wq4euZY7idsonoM NEbxIXK23iAKwl75hLiN9KDaXWTzo7wBpQze/6PDtz+l4n6zj0Ig9SRGIXAQ3+NW HjRDUBn0gXA0TTrSzP9F7/3nHX7khHjD87NxguFjiYRJCuEWNCIgqMkVb1Rgrag0 WOlH+Rn0BJM0dedBRgdGvGnwvZouDpEdqimvQ0JD93PEun/x1yFy4t/U4EWI+RM7 V9QiZ2kIgH/EbF4fkt7R+9Y86w5ZNn4YNbyP42zx5b/x0gcWzcU/yP/JPhsAP7gM EgzbTKW6KDqUQQtKn/7taHgpje/XK5AVtcqt7HbM46tF6koIUqTncSrEqnV7tAHy yagAqn4pQjs7m4Yd2Vk6jhVXM5x5vGqrRZUHQjroeX++vmetTjclNyMd6P9DIP+j +kCoG85UpPraCLHiQcu9 =WVh1 -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200528-pull-request' into staging hw/dispaly/sm501: bugfixes, add sanity checks. hw/display: use tracepoints, misc cleanups. # gpg: Signature made Thu 28 May 2020 13:35:32 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/vga-20200528-pull-request: (21 commits) sm501: Remove obsolete changelog and todo comment sm501: Optimize small overlapping blits sm501: Replace hand written implementation with pixman where possible sm501: Clean up local variables in sm501_2d_operation sm501: Use BIT(x) macro to shorten constant sm501: Shorten long variable names in sm501_2d_operation sm501: Convert printf + abort to qemu_log_mask hw/display/pxa2xx_lcd: Replace printf() call by qemu_log_mask() hw/display/omap_dss: Replace fprintf() call by qemu_log_mask(LOG_UNIMP) hw/display/exynos4210_fimd: Use qemu_log_mask(GUEST_ERROR) hw/display/vmware_vga: Let the PCI device own its I/O MemoryRegion hw/display/vmware_vga: Replace printf() calls by qemu_log_mask(ERROR) hw/display/xlnx_dp: Replace disabled DPRINTF() by error_report() hw/display/dpcd: Convert debug printf()s to trace events hw/display/dpcd: Fix memory region size hw/display/cirrus_vga: Convert debug printf() to trace event hw/display/cirrus_vga: Use qemu_log_mask(ERROR) instead of debug printf hw/display/cirrus_vga: Use qemu_log_mask(UNIMP) instead of debug printf hw/display/cirrus_vga: Convert debug printf() to trace event hw/display/cg3: Convert debug printf()s to trace events ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
b8bee16e94
|
|
@ -35,6 +35,7 @@
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#include "hw/qdev-properties.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "trace.h"
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/* Change to 1 to enable debugging */
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#define DEBUG_CG3 0
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@ -63,12 +64,6 @@
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#define CG3_VRAM_SIZE 0x100000
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#define CG3_VRAM_OFFSET 0x800000
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#define DPRINTF(fmt, ...) do { \
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if (DEBUG_CG3) { \
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printf("CG3: " fmt , ## __VA_ARGS__); \
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} \
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} while (0)
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#define TYPE_CG3 "cgthree"
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#define CG3(obj) OBJECT_CHECK(CG3State, (obj), TYPE_CG3)
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@ -195,7 +190,8 @@ static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size)
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val = 0;
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break;
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}
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DPRINTF("read %02x from reg %" HWADDR_PRIx "\n", val, addr);
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trace_cg3_read(addr, val, size);
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return val;
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}
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@ -206,9 +202,7 @@ static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val,
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uint8_t regval;
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int i;
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DPRINTF("write %" PRIx64 " to reg %" HWADDR_PRIx " size %d\n",
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val, addr, size);
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trace_cg3_write(addr, val, size);
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switch (addr) {
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case CG3_REG_BT458_ADDR:
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s->dac_index = val;
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@ -35,6 +35,7 @@
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#include "qemu/osdep.h"
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#include "qemu/module.h"
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#include "qemu/units.h"
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#include "qemu/log.h"
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#include "sysemu/reset.h"
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#include "qapi/error.h"
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#include "trace.h"
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@ -52,7 +53,6 @@
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*/
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//#define DEBUG_CIRRUS
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//#define DEBUG_BITBLT
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/***************************************
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*
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@ -905,9 +905,8 @@ static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
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static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
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{
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/* XXX */
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#ifdef DEBUG_BITBLT
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printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
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#endif
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qemu_log_mask(LOG_UNIMP,
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"cirrus: bitblt (video to cpu) is not implemented\n");
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return 0;
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}
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@ -950,19 +949,16 @@ static void cirrus_bitblt_start(CirrusVGAState * s)
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s->cirrus_blt_dstaddr &= s->cirrus_addr_mask;
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s->cirrus_blt_srcaddr &= s->cirrus_addr_mask;
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#ifdef DEBUG_BITBLT
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printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
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blt_rop,
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s->cirrus_blt_mode,
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s->cirrus_blt_modeext,
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s->cirrus_blt_width,
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s->cirrus_blt_height,
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s->cirrus_blt_dstpitch,
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s->cirrus_blt_srcpitch,
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s->cirrus_blt_dstaddr,
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s->cirrus_blt_srcaddr,
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s->vga.gr[0x2f]);
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#endif
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trace_vga_cirrus_bitblt_start(blt_rop,
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s->cirrus_blt_mode,
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s->cirrus_blt_modeext,
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s->cirrus_blt_width,
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s->cirrus_blt_height,
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s->cirrus_blt_dstpitch,
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s->cirrus_blt_srcpitch,
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s->cirrus_blt_dstaddr,
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s->cirrus_blt_srcaddr,
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s->vga.gr[0x2f]);
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switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
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case CIRRUS_BLTMODE_PIXELWIDTH8:
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@ -978,9 +974,8 @@ static void cirrus_bitblt_start(CirrusVGAState * s)
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s->cirrus_blt_pixelwidth = 4;
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break;
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default:
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#ifdef DEBUG_BITBLT
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printf("cirrus: bitblt - pixel width is unknown\n");
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#endif
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qemu_log_mask(LOG_GUEST_ERROR,
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"cirrus: bitblt - pixel width is unknown\n");
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goto bitblt_ignore;
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}
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s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
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@ -989,9 +984,8 @@ static void cirrus_bitblt_start(CirrusVGAState * s)
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cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
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CIRRUS_BLTMODE_MEMSYSDEST))
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== (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
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#ifdef DEBUG_BITBLT
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printf("cirrus: bitblt - memory-to-memory copy is requested\n");
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#endif
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qemu_log_mask(LOG_UNIMP,
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"cirrus: bitblt - memory-to-memory copy requested\n");
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goto bitblt_ignore;
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}
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@ -1038,7 +1032,9 @@ static void cirrus_bitblt_start(CirrusVGAState * s)
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} else {
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if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
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if (s->cirrus_blt_pixelwidth > 2) {
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printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
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qemu_log_mask(LOG_GUEST_ERROR,
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"cirrus: src transparent without colorexpand "
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"must be 8bpp or 16bpp\n");
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goto bitblt_ignore;
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}
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if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
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@ -1136,10 +1132,9 @@ static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
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ret = 16;
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break; /* XGA HiColor */
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default:
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#ifdef DEBUG_CIRRUS
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printf("cirrus: invalid DAC value %x in 16bpp\n",
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(s->cirrus_hidden_dac_data & 0xf));
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#endif
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qemu_log_mask(LOG_GUEST_ERROR,
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"cirrus: invalid DAC value 0x%x in 16bpp\n",
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(s->cirrus_hidden_dac_data & 0xf));
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ret = 15; /* XXX */
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break;
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}
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@ -1308,11 +1303,9 @@ static int cirrus_vga_read_sr(CirrusVGAState * s)
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#endif
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return s->vga.sr[s->vga.sr_index];
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default:
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#ifdef DEBUG_CIRRUS
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printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
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#endif
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qemu_log_mask(LOG_GUEST_ERROR,
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"cirrus: inport sr_index 0x%02x\n", s->vga.sr_index);
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return 0xff;
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break;
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}
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}
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@ -1401,10 +1394,9 @@ static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
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cirrus_update_memory_access(s);
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break;
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default:
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#ifdef DEBUG_CIRRUS
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printf("cirrus: outport sr_index %02x, sr_value %02x\n",
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s->vga.sr_index, val);
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#endif
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qemu_log_mask(LOG_GUEST_ERROR,
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"cirrus: outport sr_index 0x%02x, sr_value 0x%02x\n",
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s->vga.sr_index, val);
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break;
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}
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}
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@ -1502,9 +1494,8 @@ static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
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if (reg_index < 0x3a) {
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return s->vga.gr[reg_index];
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} else {
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#ifdef DEBUG_CIRRUS
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printf("cirrus: inport gr_index %02x\n", reg_index);
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#endif
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qemu_log_mask(LOG_GUEST_ERROR,
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"cirrus: inport gr_index 0x%02x\n", reg_index);
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return 0xff;
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}
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}
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@ -1512,9 +1503,7 @@ static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
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static void
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cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
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{
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#if defined(DEBUG_BITBLT) && 0
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printf("gr%02x: %02x\n", reg_index, reg_value);
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#endif
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trace_vga_cirrus_write_gr(reg_index, reg_value);
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switch (reg_index) {
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case 0x00: // Standard VGA, BGCOLOR 0x000000ff
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s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
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@ -1593,10 +1582,9 @@ cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
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cirrus_write_bitblt(s, reg_value);
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break;
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default:
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#ifdef DEBUG_CIRRUS
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printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
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reg_value);
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#endif
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qemu_log_mask(LOG_GUEST_ERROR,
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"cirrus: outport gr_index 0x%02x, gr_value 0x%02x\n",
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reg_index, reg_value);
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break;
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}
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}
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@ -1651,9 +1639,8 @@ static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
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return s->vga.ar_index & 0x3f;
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break;
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default:
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#ifdef DEBUG_CIRRUS
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printf("cirrus: inport cr_index %02x\n", reg_index);
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#endif
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qemu_log_mask(LOG_GUEST_ERROR,
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"cirrus: inport cr_index 0x%02x\n", reg_index);
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return 0xff;
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}
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}
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@ -1724,10 +1711,9 @@ static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
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break;
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case 0x25: // Part Status
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default:
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#ifdef DEBUG_CIRRUS
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printf("cirrus: outport cr_index %02x, cr_value %02x\n",
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s->vga.cr_index, reg_value);
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#endif
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qemu_log_mask(LOG_GUEST_ERROR,
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"cirrus: outport cr_index 0x%02x, cr_value 0x%02x\n",
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s->vga.cr_index, reg_value);
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break;
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}
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}
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|
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@ -1837,9 +1823,8 @@ static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
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value = cirrus_vga_read_gr(s, 0x31);
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break;
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default:
|
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#ifdef DEBUG_CIRRUS
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printf("cirrus: mmio read - address 0x%04x\n", address);
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#endif
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qemu_log_mask(LOG_GUEST_ERROR,
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"cirrus: mmio read - address 0x%04x\n", address);
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break;
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}
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|
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|
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@ -1949,10 +1934,9 @@ static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
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cirrus_vga_write_gr(s, 0x31, value);
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||||
break;
|
||||
default:
|
||||
#ifdef DEBUG_CIRRUS
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printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
|
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address, value);
|
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#endif
|
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qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
|
||||
address, value);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -2050,9 +2034,8 @@ static uint64_t cirrus_vga_mem_read(void *opaque,
|
|||
}
|
||||
} else {
|
||||
val = 0xff;
|
||||
#ifdef DEBUG_CIRRUS
|
||||
printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
|
||||
#endif
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"cirrus: mem_readb 0x" TARGET_FMT_plx "\n", addr);
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
|
@ -2115,10 +2098,9 @@ static void cirrus_vga_mem_write(void *opaque,
|
|||
cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
|
||||
}
|
||||
} else {
|
||||
#ifdef DEBUG_CIRRUS
|
||||
printf("cirrus: mem_writeb " TARGET_FMT_plx " value 0x%02" PRIu64 "\n", addr,
|
||||
mem_value);
|
||||
#endif
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"cirrus: mem_writeb 0x" TARGET_FMT_plx " "
|
||||
"value 0x%02" PRIu64 "\n", addr, mem_value);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2414,6 +2396,9 @@ static uint64_t cirrus_linear_bitblt_read(void *opaque,
|
|||
|
||||
/* XXX handle bitblt */
|
||||
(void)s;
|
||||
qemu_log_mask(LOG_UNIMP,
|
||||
"cirrus: linear bitblt is not implemented\n");
|
||||
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* dpcd.c
|
||||
* Xilinx Display Port Control Data
|
||||
*
|
||||
* Copyright (C) 2015 : GreenSocs Ltd
|
||||
* http://www.greensocs.com/ , email: info@greensocs.com
|
||||
|
|
@ -32,16 +32,7 @@
|
|||
#include "hw/misc/auxbus.h"
|
||||
#include "migration/vmstate.h"
|
||||
#include "hw/display/dpcd.h"
|
||||
|
||||
#ifndef DEBUG_DPCD
|
||||
#define DEBUG_DPCD 0
|
||||
#endif
|
||||
|
||||
#define DPRINTF(fmt, ...) do { \
|
||||
if (DEBUG_DPCD) { \
|
||||
qemu_log("dpcd: " fmt, ## __VA_ARGS__); \
|
||||
} \
|
||||
} while (0)
|
||||
#include "trace.h"
|
||||
|
||||
#define DPCD_READABLE_AREA 0x600
|
||||
|
||||
|
|
@ -70,8 +61,8 @@ static uint64_t dpcd_read(void *opaque, hwaddr offset, unsigned size)
|
|||
offset);
|
||||
ret = 0;
|
||||
}
|
||||
trace_dpcd_read(offset, ret);
|
||||
|
||||
DPRINTF("read 0x%" PRIX8 " @0x%" HWADDR_PRIX "\n", ret, offset);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -80,8 +71,7 @@ static void dpcd_write(void *opaque, hwaddr offset, uint64_t value,
|
|||
{
|
||||
DPCDState *e = DPCD(opaque);
|
||||
|
||||
DPRINTF("write 0x%" PRIX8 " @0x%" HWADDR_PRIX "\n", (uint8_t)value, offset);
|
||||
|
||||
trace_dpcd_write(offset, value);
|
||||
if (offset < DPCD_READABLE_AREA) {
|
||||
e->dpcd_info[offset] = value;
|
||||
} else {
|
||||
|
|
@ -137,7 +127,7 @@ static void dpcd_init(Object *obj)
|
|||
{
|
||||
DPCDState *s = DPCD(obj);
|
||||
|
||||
memory_region_init_io(&s->iomem, obj, &aux_ops, s, TYPE_DPCD, 0x7FFFF);
|
||||
memory_region_init_io(&s->iomem, obj, &aux_ops, s, TYPE_DPCD, 0x80000);
|
||||
aux_init_mmio(AUX_SLAVE(obj), &s->iomem);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@
|
|||
#include "ui/pixel_ops.h"
|
||||
#include "qemu/bswap.h"
|
||||
#include "qemu/module.h"
|
||||
#include "qemu/log.h"
|
||||
|
||||
/* Debug messages configuration */
|
||||
#define EXYNOS4210_FIMD_DEBUG 0
|
||||
|
|
@ -39,20 +40,15 @@
|
|||
#if EXYNOS4210_FIMD_DEBUG == 0
|
||||
#define DPRINT_L1(fmt, args...) do { } while (0)
|
||||
#define DPRINT_L2(fmt, args...) do { } while (0)
|
||||
#define DPRINT_ERROR(fmt, args...) do { } while (0)
|
||||
#elif EXYNOS4210_FIMD_DEBUG == 1
|
||||
#define DPRINT_L1(fmt, args...) \
|
||||
do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
|
||||
#define DPRINT_L2(fmt, args...) do { } while (0)
|
||||
#define DPRINT_ERROR(fmt, args...) \
|
||||
do {fprintf(stderr, "QEMU FIMD ERROR: "fmt, ## args); } while (0)
|
||||
#else
|
||||
#define DPRINT_L1(fmt, args...) \
|
||||
do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
|
||||
#define DPRINT_L2(fmt, args...) \
|
||||
do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
|
||||
#define DPRINT_ERROR(fmt, args...) \
|
||||
do {fprintf(stderr, "QEMU FIMD ERROR: "fmt, ## args); } while (0)
|
||||
#endif
|
||||
|
||||
#if EXYNOS4210_FIMD_MODE_TRACE == 0
|
||||
|
|
@ -1108,7 +1104,7 @@ static inline int fimd_get_buffer_id(Exynos4210fimdWindow *w)
|
|||
case FIMD_WINCON_BUF2_STAT:
|
||||
return 2;
|
||||
default:
|
||||
DPRINT_ERROR("Non-existent buffer index\n");
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "FIMD: Non-existent buffer index\n");
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
|
@ -1160,20 +1156,24 @@ static void fimd_update_memory_section(Exynos4210fimdState *s, unsigned win)
|
|||
|
||||
if (int128_get64(w->mem_section.size) != w->fb_len ||
|
||||
!memory_region_is_ram(w->mem_section.mr)) {
|
||||
DPRINT_ERROR("Failed to find window %u framebuffer region\n", win);
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"FIMD: Failed to find window %u framebuffer region\n",
|
||||
win);
|
||||
goto error_return;
|
||||
}
|
||||
|
||||
w->host_fb_addr = cpu_physical_memory_map(fb_start_addr, &fb_mapped_len,
|
||||
false);
|
||||
if (!w->host_fb_addr) {
|
||||
DPRINT_ERROR("Failed to map window %u framebuffer\n", win);
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"FIMD: Failed to map window %u framebuffer\n", win);
|
||||
goto error_return;
|
||||
}
|
||||
|
||||
if (fb_mapped_len != w->fb_len) {
|
||||
DPRINT_ERROR("Window %u mapped framebuffer length is less then "
|
||||
"expected\n", win);
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"FIMD: Window %u mapped framebuffer length is less than "
|
||||
"expected\n", win);
|
||||
cpu_physical_memory_unmap(w->host_fb_addr, fb_mapped_len, 0, 0);
|
||||
goto error_return;
|
||||
}
|
||||
|
|
@ -1490,7 +1490,9 @@ static void exynos4210_fimd_write(void *opaque, hwaddr offset,
|
|||
break;
|
||||
case 3:
|
||||
if (w != 1 && w != 2) {
|
||||
DPRINT_ERROR("Bad write offset 0x%08x\n", offset);
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"FIMD: Bad write offset 0x%08"HWADDR_PRIx"\n",
|
||||
offset);
|
||||
return;
|
||||
}
|
||||
s->window[w].osdsize = val;
|
||||
|
|
@ -1624,7 +1626,9 @@ static void exynos4210_fimd_write(void *opaque, hwaddr offset,
|
|||
break;
|
||||
case FIMD_VIDW0ADD0_B2 ... FIMD_VIDW4ADD0_B2:
|
||||
if (offset & 0x0004) {
|
||||
DPRINT_ERROR("bad write offset 0x%08x\n", offset);
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"FIMD: bad write offset 0x%08"HWADDR_PRIx"\n",
|
||||
offset);
|
||||
break;
|
||||
}
|
||||
w = (offset - FIMD_VIDW0ADD0_B2) >> 3;
|
||||
|
|
@ -1638,14 +1642,18 @@ static void exynos4210_fimd_write(void *opaque, hwaddr offset,
|
|||
break;
|
||||
case FIMD_SHD_ADD0_START ... FIMD_SHD_ADD0_END:
|
||||
if (offset & 0x0004) {
|
||||
DPRINT_ERROR("bad write offset 0x%08x\n", offset);
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"FIMD: bad write offset 0x%08"HWADDR_PRIx"\n",
|
||||
offset);
|
||||
break;
|
||||
}
|
||||
s->window[(offset - FIMD_SHD_ADD0_START) >> 3].shadow_buf_start = val;
|
||||
break;
|
||||
case FIMD_SHD_ADD1_START ... FIMD_SHD_ADD1_END:
|
||||
if (offset & 0x0004) {
|
||||
DPRINT_ERROR("bad write offset 0x%08x\n", offset);
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"FIMD: bad write offset 0x%08"HWADDR_PRIx"\n",
|
||||
offset);
|
||||
break;
|
||||
}
|
||||
s->window[(offset - FIMD_SHD_ADD1_START) >> 3].shadow_buf_end = val;
|
||||
|
|
@ -1665,7 +1673,8 @@ static void exynos4210_fimd_write(void *opaque, hwaddr offset,
|
|||
s->window[w].palette[i] = val;
|
||||
break;
|
||||
default:
|
||||
DPRINT_ERROR("bad write offset 0x%08x\n", offset);
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"FIMD: bad write offset 0x%08"HWADDR_PRIx"\n", offset);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -1715,7 +1724,9 @@ static uint64_t exynos4210_fimd_read(void *opaque, hwaddr offset,
|
|||
break;
|
||||
case 3:
|
||||
if (w != 1 && w != 2) {
|
||||
DPRINT_ERROR("bad read offset 0x%08x\n", offset);
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"FIMD: bad read offset 0x%08"HWADDR_PRIx"\n",
|
||||
offset);
|
||||
return 0xBAADBAAD;
|
||||
}
|
||||
ret = s->window[w].osdsize;
|
||||
|
|
@ -1809,7 +1820,8 @@ static uint64_t exynos4210_fimd_read(void *opaque, hwaddr offset,
|
|||
return s->window[w].palette[i];
|
||||
}
|
||||
|
||||
DPRINT_ERROR("bad read offset 0x%08x\n", offset);
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"FIMD: bad read offset 0x%08"HWADDR_PRIx"\n", offset);
|
||||
return 0xBAADBAAD;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -619,7 +619,7 @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s)
|
|||
if (s->rfbi.control & (1 << 1)) { /* BYPASS */
|
||||
/* TODO: in non-Bypass mode we probably need to just assert the
|
||||
* DRQ and wait for DMA to write the pixels. */
|
||||
fprintf(stderr, "%s: Bypass mode unimplemented\n", __func__);
|
||||
qemu_log_mask(LOG_UNIMP, "%s: Bypass mode unimplemented\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -426,9 +426,10 @@ static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,
|
|||
if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB))
|
||||
s->status[0] |= LCSR0_QD;
|
||||
|
||||
if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT))
|
||||
printf("%s: internal frame buffer unsupported\n", __func__);
|
||||
|
||||
if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT)) {
|
||||
qemu_log_mask(LOG_UNIMP,
|
||||
"%s: internal frame buffer unsupported\n", __func__);
|
||||
}
|
||||
if ((s->control[3] & LCCR3_API) &&
|
||||
(value & LCCR0_ENB) && !(value & LCCR0_LCDT))
|
||||
s->status[0] |= LCSR0_ABC;
|
||||
|
|
@ -462,9 +463,9 @@ static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,
|
|||
break;
|
||||
|
||||
case OVL1C1:
|
||||
if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN))
|
||||
printf("%s: Overlay 1 not supported\n", __func__);
|
||||
|
||||
if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN)) {
|
||||
qemu_log_mask(LOG_UNIMP, "%s: Overlay 1 not supported\n", __func__);
|
||||
}
|
||||
s->ovl1c[0] = value & 0x80ffffff;
|
||||
s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS);
|
||||
break;
|
||||
|
|
@ -474,9 +475,9 @@ static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,
|
|||
break;
|
||||
|
||||
case OVL2C1:
|
||||
if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN))
|
||||
printf("%s: Overlay 2 not supported\n", __func__);
|
||||
|
||||
if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN)) {
|
||||
qemu_log_mask(LOG_UNIMP, "%s: Overlay 2 not supported\n", __func__);
|
||||
}
|
||||
s->ovl2c[0] = value & 0x80ffffff;
|
||||
s->dma_ch[2].up = !!(value & OVLC1_EN);
|
||||
s->dma_ch[3].up = !!(value & OVLC1_EN);
|
||||
|
|
@ -488,9 +489,10 @@ static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,
|
|||
break;
|
||||
|
||||
case CCR:
|
||||
if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
|
||||
printf("%s: Hardware cursor unimplemented\n", __func__);
|
||||
|
||||
if (!(s->ccr & CCR_CEN) && (value & CCR_CEN)) {
|
||||
qemu_log_mask(LOG_UNIMP,
|
||||
"%s: Hardware cursor unimplemented\n", __func__);
|
||||
}
|
||||
s->ccr = value & 0x81ffffe7;
|
||||
s->dma_ch[5].up = !!(value & CCR_CEN);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
* QEMU SM501 Device
|
||||
*
|
||||
* Copyright (c) 2008 Shin-ichiro KAWASAKI
|
||||
* Copyright (c) 2016 BALATON Zoltan
|
||||
* Copyright (c) 2016-2020 BALATON Zoltan
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
|
|
@ -40,23 +40,6 @@
|
|||
#include "ui/pixel_ops.h"
|
||||
#include "qemu/bswap.h"
|
||||
|
||||
/*
|
||||
* Status: 2010/05/07
|
||||
* - Minimum implementation for Linux console : mmio regs and CRT layer.
|
||||
* - 2D graphics acceleration partially supported : only fill rectangle.
|
||||
*
|
||||
* Status: 2016/12/04
|
||||
* - Misc fixes: endianness, hardware cursor
|
||||
* - Panel support
|
||||
*
|
||||
* TODO:
|
||||
* - Touch panel support
|
||||
* - USB support
|
||||
* - UART support
|
||||
* - More 2D graphics engine support
|
||||
* - Performance tuning
|
||||
*/
|
||||
|
||||
/*#define DEBUG_SM501*/
|
||||
/*#define DEBUG_BITBLT*/
|
||||
|
||||
|
|
@ -699,139 +682,176 @@ static inline void hwc_invalidate(SM501State *s, int crt)
|
|||
|
||||
static void sm501_2d_operation(SM501State *s)
|
||||
{
|
||||
/* obtain operation parameters */
|
||||
int operation = (s->twoD_control >> 16) & 0x1f;
|
||||
int rtl = s->twoD_control & 0x8000000;
|
||||
int src_x = (s->twoD_source >> 16) & 0x01FFF;
|
||||
int src_y = s->twoD_source & 0xFFFF;
|
||||
int dst_x = (s->twoD_destination >> 16) & 0x01FFF;
|
||||
int dst_y = s->twoD_destination & 0xFFFF;
|
||||
int operation_width = (s->twoD_dimension >> 16) & 0x1FFF;
|
||||
int operation_height = s->twoD_dimension & 0xFFFF;
|
||||
uint32_t color = s->twoD_foreground;
|
||||
int format_flags = (s->twoD_stretch >> 20) & 0x3;
|
||||
int addressing = (s->twoD_stretch >> 16) & 0xF;
|
||||
int cmd = (s->twoD_control >> 16) & 0x1F;
|
||||
int rtl = s->twoD_control & BIT(27);
|
||||
int format = (s->twoD_stretch >> 20) & 0x3;
|
||||
int rop_mode = (s->twoD_control >> 15) & 0x1; /* 1 for rop2, else rop3 */
|
||||
/* 1 if rop2 source is the pattern, otherwise the source is the bitmap */
|
||||
int rop2_source_is_pattern = (s->twoD_control >> 14) & 0x1;
|
||||
int rop = s->twoD_control & 0xFF;
|
||||
uint32_t src_base = s->twoD_source_base & 0x03FFFFFF;
|
||||
unsigned int dst_x = (s->twoD_destination >> 16) & 0x01FFF;
|
||||
unsigned int dst_y = s->twoD_destination & 0xFFFF;
|
||||
unsigned int width = (s->twoD_dimension >> 16) & 0x1FFF;
|
||||
unsigned int height = s->twoD_dimension & 0xFFFF;
|
||||
uint32_t dst_base = s->twoD_destination_base & 0x03FFFFFF;
|
||||
|
||||
/* get frame buffer info */
|
||||
uint8_t *src = s->local_mem + src_base;
|
||||
uint8_t *dst = s->local_mem + dst_base;
|
||||
int src_width = s->twoD_pitch & 0x1FFF;
|
||||
int dst_width = (s->twoD_pitch >> 16) & 0x1FFF;
|
||||
unsigned int dst_pitch = (s->twoD_pitch >> 16) & 0x1FFF;
|
||||
int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0;
|
||||
int fb_len = get_width(s, crt) * get_height(s, crt) * get_bpp(s, crt);
|
||||
|
||||
if (addressing != 0x0) {
|
||||
printf("%s: only XY addressing is supported.\n", __func__);
|
||||
abort();
|
||||
if ((s->twoD_stretch >> 16) & 0xF) {
|
||||
qemu_log_mask(LOG_UNIMP, "sm501: only XY addressing is supported.\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (rop_mode == 0) {
|
||||
if (rop != 0xcc) {
|
||||
/* Anything other than plain copies are not supported */
|
||||
qemu_log_mask(LOG_UNIMP, "sm501: rop3 mode with rop %x is not "
|
||||
"supported.\n", rop);
|
||||
if (s->twoD_source_base & BIT(27) || s->twoD_destination_base & BIT(27)) {
|
||||
qemu_log_mask(LOG_UNIMP, "sm501: only local memory is supported.\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (!dst_pitch) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "sm501: Zero dest pitch.\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (!width || !height) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "sm501: Zero size 2D op.\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (rtl) {
|
||||
dst_x -= width - 1;
|
||||
dst_y -= height - 1;
|
||||
}
|
||||
|
||||
if (dst_base >= get_local_mem_size(s) || dst_base +
|
||||
(dst_x + width + (dst_y + height) * (dst_pitch + width)) *
|
||||
(1 << format) >= get_local_mem_size(s)) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "sm501: 2D op dest is outside vram.\n");
|
||||
return;
|
||||
}
|
||||
|
||||
switch (cmd) {
|
||||
case 0: /* BitBlt */
|
||||
{
|
||||
static uint32_t tmp_buf[16384];
|
||||
unsigned int src_x = (s->twoD_source >> 16) & 0x01FFF;
|
||||
unsigned int src_y = s->twoD_source & 0xFFFF;
|
||||
uint32_t src_base = s->twoD_source_base & 0x03FFFFFF;
|
||||
unsigned int src_pitch = s->twoD_pitch & 0x1FFF;
|
||||
|
||||
if (!src_pitch) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "sm501: Zero src pitch.\n");
|
||||
return;
|
||||
}
|
||||
} else {
|
||||
if (rop2_source_is_pattern && rop != 0x5) {
|
||||
/* For pattern source, we support only inverse dest */
|
||||
qemu_log_mask(LOG_UNIMP, "sm501: rop2 source being the pattern and "
|
||||
"rop %x is not supported.\n", rop);
|
||||
|
||||
if (rtl) {
|
||||
src_x -= width - 1;
|
||||
src_y -= height - 1;
|
||||
}
|
||||
|
||||
if (src_base >= get_local_mem_size(s) || src_base +
|
||||
(src_x + width + (src_y + height) * (src_pitch + width)) *
|
||||
(1 << format) >= get_local_mem_size(s)) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"sm501: 2D op src is outside vram.\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if ((rop_mode && rop == 0x5) || (!rop_mode && rop == 0x55)) {
|
||||
/* Invert dest, is there a way to do this with pixman? */
|
||||
unsigned int x, y, i;
|
||||
uint8_t *d = s->local_mem + dst_base;
|
||||
|
||||
for (y = 0; y < height; y++) {
|
||||
i = (dst_x + (dst_y + y) * dst_pitch) * (1 << format);
|
||||
for (x = 0; x < width; x++, i += (1 << format)) {
|
||||
switch (format) {
|
||||
case 0:
|
||||
d[i] = ~d[i];
|
||||
break;
|
||||
case 1:
|
||||
*(uint16_t *)&d[i] = ~*(uint16_t *)&d[i];
|
||||
break;
|
||||
case 2:
|
||||
*(uint32_t *)&d[i] = ~*(uint32_t *)&d[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (rop != 0x5 && rop != 0xc) {
|
||||
/* Anything other than plain copies or inverse dest is not
|
||||
* supported */
|
||||
qemu_log_mask(LOG_UNIMP, "sm501: rop mode %x is not "
|
||||
"supported.\n", rop);
|
||||
/* Do copy src for unimplemented ops, better than unpainted area */
|
||||
if ((rop_mode && (rop != 0xc || rop2_source_is_pattern)) ||
|
||||
(!rop_mode && rop != 0xcc)) {
|
||||
qemu_log_mask(LOG_UNIMP,
|
||||
"sm501: rop%d op %x%s not implemented\n",
|
||||
(rop_mode ? 2 : 3), rop,
|
||||
(rop2_source_is_pattern ?
|
||||
" with pattern source" : ""));
|
||||
}
|
||||
/* Check for overlaps, this could be made more exact */
|
||||
uint32_t sb, se, db, de;
|
||||
sb = src_base + src_x + src_y * (width + src_pitch);
|
||||
se = sb + width + height * (width + src_pitch);
|
||||
db = dst_base + dst_x + dst_y * (width + dst_pitch);
|
||||
de = db + width + height * (width + dst_pitch);
|
||||
if (rtl && ((db >= sb && db <= se) || (de >= sb && de <= se))) {
|
||||
/* regions may overlap: copy via temporary */
|
||||
int free_buf = 0, llb = width * (1 << format);
|
||||
int tmp_stride = DIV_ROUND_UP(llb, sizeof(uint32_t));
|
||||
uint32_t *tmp = tmp_buf;
|
||||
|
||||
if (tmp_stride * sizeof(uint32_t) * height > sizeof(tmp_buf)) {
|
||||
tmp = g_malloc(tmp_stride * sizeof(uint32_t) * height);
|
||||
free_buf = 1;
|
||||
}
|
||||
pixman_blt((uint32_t *)&s->local_mem[src_base], tmp,
|
||||
src_pitch * (1 << format) / sizeof(uint32_t),
|
||||
tmp_stride, 8 * (1 << format), 8 * (1 << format),
|
||||
src_x, src_y, 0, 0, width, height);
|
||||
pixman_blt(tmp, (uint32_t *)&s->local_mem[dst_base],
|
||||
tmp_stride,
|
||||
dst_pitch * (1 << format) / sizeof(uint32_t),
|
||||
8 * (1 << format), 8 * (1 << format),
|
||||
0, 0, dst_x, dst_y, width, height);
|
||||
if (free_buf) {
|
||||
g_free(tmp);
|
||||
}
|
||||
} else {
|
||||
pixman_blt((uint32_t *)&s->local_mem[src_base],
|
||||
(uint32_t *)&s->local_mem[dst_base],
|
||||
src_pitch * (1 << format) / sizeof(uint32_t),
|
||||
dst_pitch * (1 << format) / sizeof(uint32_t),
|
||||
8 * (1 << format), 8 * (1 << format),
|
||||
src_x, src_y, dst_x, dst_y, width, height);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if ((s->twoD_source_base & 0x08000000) ||
|
||||
(s->twoD_destination_base & 0x08000000)) {
|
||||
printf("%s: only local memory is supported.\n", __func__);
|
||||
abort();
|
||||
}
|
||||
|
||||
switch (operation) {
|
||||
case 0x00: /* copy area */
|
||||
#define COPY_AREA(_bpp, _pixel_type, rtl) { \
|
||||
int y, x, index_d, index_s; \
|
||||
for (y = 0; y < operation_height; y++) { \
|
||||
for (x = 0; x < operation_width; x++) { \
|
||||
_pixel_type val; \
|
||||
\
|
||||
if (rtl) { \
|
||||
index_s = ((src_y - y) * src_width + src_x - x) * _bpp; \
|
||||
index_d = ((dst_y - y) * dst_width + dst_x - x) * _bpp; \
|
||||
} else { \
|
||||
index_s = ((src_y + y) * src_width + src_x + x) * _bpp; \
|
||||
index_d = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \
|
||||
} \
|
||||
if (rop_mode == 1 && rop == 5) { \
|
||||
/* Invert dest */ \
|
||||
val = ~*(_pixel_type *)&dst[index_d]; \
|
||||
} else { \
|
||||
val = *(_pixel_type *)&src[index_s]; \
|
||||
} \
|
||||
*(_pixel_type *)&dst[index_d] = val; \
|
||||
} \
|
||||
} \
|
||||
}
|
||||
switch (format_flags) {
|
||||
case 0:
|
||||
COPY_AREA(1, uint8_t, rtl);
|
||||
break;
|
||||
case 1:
|
||||
COPY_AREA(2, uint16_t, rtl);
|
||||
break;
|
||||
case 2:
|
||||
COPY_AREA(4, uint32_t, rtl);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x01: /* fill rectangle */
|
||||
#define FILL_RECT(_bpp, _pixel_type) { \
|
||||
int y, x; \
|
||||
for (y = 0; y < operation_height; y++) { \
|
||||
for (x = 0; x < operation_width; x++) { \
|
||||
int index = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \
|
||||
*(_pixel_type *)&dst[index] = (_pixel_type)color; \
|
||||
} \
|
||||
} \
|
||||
}
|
||||
case 1: /* Rectangle Fill */
|
||||
{
|
||||
uint32_t color = s->twoD_foreground;
|
||||
|
||||
switch (format_flags) {
|
||||
case 0:
|
||||
FILL_RECT(1, uint8_t);
|
||||
break;
|
||||
case 1:
|
||||
color = cpu_to_le16(color);
|
||||
FILL_RECT(2, uint16_t);
|
||||
break;
|
||||
case 2:
|
||||
if (format == 2) {
|
||||
color = cpu_to_le32(color);
|
||||
FILL_RECT(4, uint32_t);
|
||||
break;
|
||||
} else if (format == 1) {
|
||||
color = cpu_to_le16(color);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
printf("non-implemented SM501 2D operation. %d\n", operation);
|
||||
abort();
|
||||
pixman_fill((uint32_t *)&s->local_mem[dst_base],
|
||||
dst_pitch * (1 << format) / sizeof(uint32_t),
|
||||
8 * (1 << format), dst_x, dst_y, width, height, color);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
qemu_log_mask(LOG_UNIMP, "sm501: not implemented 2D operation: %d\n",
|
||||
cmd);
|
||||
return;
|
||||
}
|
||||
|
||||
if (dst_base >= get_fb_addr(s, crt) &&
|
||||
dst_base <= get_fb_addr(s, crt) + fb_len) {
|
||||
int dst_len = MIN(fb_len, ((dst_y + operation_height - 1) * dst_width +
|
||||
dst_x + operation_width) * (1 << format_flags));
|
||||
int dst_len = MIN(fb_len, ((dst_y + height - 1) * dst_pitch +
|
||||
dst_x + width) * (1 << format));
|
||||
if (dst_len) {
|
||||
memory_region_set_dirty(&s->local_mem_region, dst_base, dst_len);
|
||||
}
|
||||
|
|
@ -892,9 +912,8 @@ static uint64_t sm501_system_config_read(void *opaque, hwaddr addr,
|
|||
break;
|
||||
|
||||
default:
|
||||
printf("sm501 system config : not implemented register read."
|
||||
" addr=%x\n", (int)addr);
|
||||
abort();
|
||||
qemu_log_mask(LOG_UNIMP, "sm501: not implemented system config"
|
||||
"register read. addr=%" HWADDR_PRIx "\n", addr);
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
|
@ -948,15 +967,15 @@ static void sm501_system_config_write(void *opaque, hwaddr addr,
|
|||
break;
|
||||
case SM501_ENDIAN_CONTROL:
|
||||
if (value & 0x00000001) {
|
||||
printf("sm501 system config : big endian mode not implemented.\n");
|
||||
abort();
|
||||
qemu_log_mask(LOG_UNIMP, "sm501: system config big endian mode not"
|
||||
" implemented.\n");
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
printf("sm501 system config : not implemented register write."
|
||||
" addr=%x, val=%x\n", (int)addr, (uint32_t)value);
|
||||
abort();
|
||||
qemu_log_mask(LOG_UNIMP, "sm501: not implemented system config"
|
||||
"register write. addr=%" HWADDR_PRIx
|
||||
", val=%" PRIx64 "\n", addr, value);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1207,9 +1226,8 @@ static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr,
|
|||
break;
|
||||
|
||||
default:
|
||||
printf("sm501 disp ctrl : not implemented register read."
|
||||
" addr=%x\n", (int)addr);
|
||||
abort();
|
||||
qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register "
|
||||
"read. addr=%" HWADDR_PRIx "\n", addr);
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
|
@ -1345,9 +1363,9 @@ static void sm501_disp_ctrl_write(void *opaque, hwaddr addr,
|
|||
break;
|
||||
|
||||
default:
|
||||
printf("sm501 disp ctrl : not implemented register write."
|
||||
" addr=%x, val=%x\n", (int)addr, (unsigned)value);
|
||||
abort();
|
||||
qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register "
|
||||
"write. addr=%" HWADDR_PRIx
|
||||
", val=%" PRIx64 "\n", addr, value);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1433,9 +1451,8 @@ static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr,
|
|||
ret = 0; /* Should return interrupt status */
|
||||
break;
|
||||
default:
|
||||
printf("sm501 disp ctrl : not implemented register read."
|
||||
" addr=%x\n", (int)addr);
|
||||
abort();
|
||||
qemu_log_mask(LOG_UNIMP, "sm501: not implemented disp ctrl register "
|
||||
"read. addr=%" HWADDR_PRIx "\n", addr);
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
|
@ -1520,9 +1537,9 @@ static void sm501_2d_engine_write(void *opaque, hwaddr addr,
|
|||
/* ignored, writing 0 should clear interrupt status */
|
||||
break;
|
||||
default:
|
||||
printf("sm501 2d engine : not implemented register write."
|
||||
" addr=%x, val=%x\n", (int)addr, (unsigned)value);
|
||||
abort();
|
||||
qemu_log_mask(LOG_UNIMP, "sm501: not implemented 2d engine register "
|
||||
"write. addr=%" HWADDR_PRIx
|
||||
", val=%" PRIx64 "\n", addr, value);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1670,9 +1687,9 @@ static void sm501_update_display(void *opaque)
|
|||
draw_line = draw_line32_funcs[dst_depth_index];
|
||||
break;
|
||||
default:
|
||||
printf("sm501 update display : invalid control register value.\n");
|
||||
abort();
|
||||
break;
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "sm501: update display"
|
||||
"invalid control register value.\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* set up to draw hardware cursor */
|
||||
|
|
|
|||
|
|
@ -133,6 +133,8 @@ vga_vbe_write(uint32_t index, uint32_t val) "index 0x%x, val 0x%x"
|
|||
vga_cirrus_read_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
|
||||
vga_cirrus_write_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
|
||||
vga_cirrus_write_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x"
|
||||
vga_cirrus_write_gr(uint8_t index, uint8_t val) "GR addr 0x%02x, val 0x%02x"
|
||||
vga_cirrus_bitblt_start(uint8_t blt_rop, uint8_t blt_mode, uint8_t blt_modeext, int blt_width, int blt_height, int blt_dstpitch, int blt_srcpitch, uint32_t blt_dstaddr, uint32_t blt_srcaddr, uint8_t gr_val) "rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08"PRIx32" saddr=0x%08"PRIx32" writemask=0x%02x"
|
||||
|
||||
# sii9022.c
|
||||
sii9022_read_reg(uint8_t addr, uint8_t val) "addr 0x%02x, val 0x%02x"
|
||||
|
|
@ -151,3 +153,11 @@ artist_vram_write(unsigned int size, uint64_t addr, uint64_t val) "%u 0x%"PRIx64
|
|||
artist_fill_window(unsigned int start_x, unsigned int start_y, unsigned int width, unsigned int height, uint32_t op, uint32_t ctlpln) "start=%ux%u length=%ux%u op=0x%08x ctlpln=0x%08x"
|
||||
artist_block_move(unsigned int start_x, unsigned int start_y, unsigned int dest_x, unsigned int dest_y, unsigned int width, unsigned int height) "source %ux%u -> dest %ux%u size %ux%u"
|
||||
artist_draw_line(unsigned int start_x, unsigned int start_y, unsigned int end_x, unsigned int end_y) "%ux%u %ux%u"
|
||||
|
||||
# cg3.c
|
||||
cg3_read(uint32_t addr, uint32_t val, unsigned size) "read addr:0x%06"PRIx32" val:0x%08"PRIx32" size:%u"
|
||||
cg3_write(uint32_t addr, uint32_t val, unsigned size) "write addr:0x%06"PRIx32" val:0x%08"PRIx32" size:%u"
|
||||
|
||||
# dpcd.c
|
||||
dpcd_read(uint32_t addr, uint8_t val) "read addr:0x%"PRIx32" val:0x%02x"
|
||||
dpcd_write(uint32_t addr, uint8_t val) "write addr:0x%"PRIx32" val:0x%02x"
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@
|
|||
#include "qemu/module.h"
|
||||
#include "qemu/units.h"
|
||||
#include "qapi/error.h"
|
||||
#include "qemu/log.h"
|
||||
#include "hw/loader.h"
|
||||
#include "trace.h"
|
||||
#include "ui/vnc.h"
|
||||
|
|
@ -953,7 +954,8 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
|
|||
ret = s->scratch[s->index - SVGA_SCRATCH_BASE];
|
||||
break;
|
||||
}
|
||||
printf("%s: Bad register %02x\n", __func__, s->index);
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"%s: Bad register %02x\n", __func__, s->index);
|
||||
ret = 0;
|
||||
break;
|
||||
}
|
||||
|
|
@ -1002,7 +1004,8 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
|
|||
s->new_width = value;
|
||||
s->invalidated = 1;
|
||||
} else {
|
||||
printf("%s: Bad width: %i\n", __func__, value);
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"%s: Bad width: %i\n", __func__, value);
|
||||
}
|
||||
break;
|
||||
|
||||
|
|
@ -1011,13 +1014,15 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
|
|||
s->new_height = value;
|
||||
s->invalidated = 1;
|
||||
} else {
|
||||
printf("%s: Bad height: %i\n", __func__, value);
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"%s: Bad height: %i\n", __func__, value);
|
||||
}
|
||||
break;
|
||||
|
||||
case SVGA_REG_BITS_PER_PIXEL:
|
||||
if (value != 32) {
|
||||
printf("%s: Bad bits per pixel: %i bits\n", __func__, value);
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"%s: Bad bits per pixel: %i bits\n", __func__, value);
|
||||
s->config = 0;
|
||||
s->invalidated = 1;
|
||||
}
|
||||
|
|
@ -1082,7 +1087,8 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
|
|||
s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
|
||||
break;
|
||||
}
|
||||
printf("%s: Bad register %02x\n", __func__, s->index);
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"%s: Bad register %02x\n", __func__, s->index);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1300,7 +1306,7 @@ static void pci_vmsvga_realize(PCIDevice *dev, Error **errp)
|
|||
dev->config[PCI_LATENCY_TIMER] = 0x40;
|
||||
dev->config[PCI_INTERRUPT_LINE] = 0xff; /* End */
|
||||
|
||||
memory_region_init_io(&s->io_bar, NULL, &vmsvga_io_ops, &s->chip,
|
||||
memory_region_init_io(&s->io_bar, OBJECT(dev), &vmsvga_io_ops, &s->chip,
|
||||
"vmsvga-io", 0x10);
|
||||
memory_region_set_flush_coalesced(&s->io_bar);
|
||||
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* xlnx_dp.c
|
||||
* Xilinx Display Port
|
||||
*
|
||||
* Copyright (C) 2015 : GreenSocs Ltd
|
||||
* http://www.greensocs.com/ , email: info@greensocs.com
|
||||
|
|
@ -24,6 +24,7 @@
|
|||
|
||||
#include "qemu/osdep.h"
|
||||
#include "qapi/error.h"
|
||||
#include "qemu/error-report.h"
|
||||
#include "qemu/log.h"
|
||||
#include "qemu/module.h"
|
||||
#include "hw/display/xlnx_dp.h"
|
||||
|
|
@ -465,7 +466,7 @@ static uint8_t xlnx_dp_aux_pop_tx_fifo(XlnxDPState *s)
|
|||
uint8_t ret;
|
||||
|
||||
if (fifo8_is_empty(&s->tx_fifo)) {
|
||||
DPRINTF("tx_fifo underflow..\n");
|
||||
error_report("%s: TX_FIFO underflow", __func__);
|
||||
abort();
|
||||
}
|
||||
ret = fifo8_pop(&s->tx_fifo);
|
||||
|
|
@ -525,6 +526,7 @@ static void xlnx_dp_aux_set_command(XlnxDPState *s, uint32_t value)
|
|||
qemu_log_mask(LOG_UNIMP, "xlnx_dp: Write i2c status not implemented\n");
|
||||
break;
|
||||
default:
|
||||
error_report("%s: invalid command: %u", __func__, cmd);
|
||||
abort();
|
||||
}
|
||||
|
||||
|
|
@ -631,8 +633,8 @@ static void xlnx_dp_change_graphic_fmt(XlnxDPState *s)
|
|||
s->g_plane.format = PIXMAN_b8g8r8;
|
||||
break;
|
||||
default:
|
||||
DPRINTF("error: unsupported graphic format %u.\n",
|
||||
s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK);
|
||||
error_report("%s: unsupported graphic format %u", __func__,
|
||||
s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK);
|
||||
abort();
|
||||
}
|
||||
|
||||
|
|
@ -647,8 +649,8 @@ static void xlnx_dp_change_graphic_fmt(XlnxDPState *s)
|
|||
s->v_plane.format = PIXMAN_x8b8g8r8;
|
||||
break;
|
||||
default:
|
||||
DPRINTF("error: unsupported video format %u.\n",
|
||||
s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK);
|
||||
error_report("%s: unsupported video format %u", __func__,
|
||||
s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK);
|
||||
abort();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
#define EDID_H
|
||||
|
||||
#include "qom/object.h"
|
||||
#include "hw/qdev-properties.h"
|
||||
|
||||
typedef struct qemu_edid_info {
|
||||
const char *vendor; /* http://www.uefi.org/pnp_id_list */
|
||||
|
|
|
|||
Loading…
Reference in a new issue