target/arm: Implement FP data-processing (2 source) for fp16
We missed all of the scalar fp16 binary operations. Cc: qemu-stable@nongnu.org Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180512003217.9105-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -5299,6 +5299,61 @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
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tcg_temp_free_i64(tcg_res);
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}
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/* Floating-point data-processing (2 source) - half precision */
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static void handle_fp_2src_half(DisasContext *s, int opcode,
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int rd, int rn, int rm)
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{
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TCGv_i32 tcg_op1;
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TCGv_i32 tcg_op2;
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TCGv_i32 tcg_res;
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TCGv_ptr fpst;
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tcg_res = tcg_temp_new_i32();
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fpst = get_fpstatus_ptr(true);
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tcg_op1 = read_fp_hreg(s, rn);
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tcg_op2 = read_fp_hreg(s, rm);
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switch (opcode) {
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case 0x0: /* FMUL */
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gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x1: /* FDIV */
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gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x2: /* FADD */
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gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x3: /* FSUB */
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gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x4: /* FMAX */
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gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x5: /* FMIN */
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gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x6: /* FMAXNM */
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gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x7: /* FMINNM */
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gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
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break;
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case 0x8: /* FNMUL */
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gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
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tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000);
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break;
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default:
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g_assert_not_reached();
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}
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write_fp_sreg(s, rd, tcg_res);
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tcg_temp_free_ptr(fpst);
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tcg_temp_free_i32(tcg_op1);
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tcg_temp_free_i32(tcg_op2);
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tcg_temp_free_i32(tcg_res);
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}
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/* Floating point data-processing (2 source)
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* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
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* +---+---+---+-----------+------+---+------+--------+-----+------+------+
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@ -5331,6 +5386,16 @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
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}
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handle_fp_2src_double(s, opcode, rd, rn, rm);
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break;
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case 3:
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if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
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unallocated_encoding(s);
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return;
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}
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if (!fp_access_check(s)) {
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return;
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}
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handle_fp_2src_half(s, opcode, rd, rn, rm);
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break;
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default:
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unallocated_encoding(s);
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}
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