intel_iommu: cleanup vtd_{do_}iommu_translate()
First, let vtd_do_iommu_translate() return a status, so that we explicitly knows whether error occured. Meanwhile, we make sure that IOMMUTLBEntry is filled in in that. Then, cleanup vtd_iommu_translate a bit. So even with PT we'll get a log now. Also, remove useless assignments. Signed-off-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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7feb51b709
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@ -1069,8 +1069,10 @@ out:
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* @devfn: The devfn, which is the combined of device and function number
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* @is_write: The access is a write operation
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* @entry: IOMMUTLBEntry that contain the addr to be translated and result
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*
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* Returns true if translation is successful, otherwise false.
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*/
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static void vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
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static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
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uint8_t devfn, hwaddr addr, bool is_write,
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IOMMUTLBEntry *entry)
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{
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@ -1104,6 +1106,7 @@ static void vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
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page_mask = iotlb_entry->mask;
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goto out;
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}
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/* Try to fetch context-entry from cache first */
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if (cc_entry->context_cache_gen == s->context_cache_gen) {
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trace_vtd_iotlb_cc_hit(bus_num, devfn, cc_entry->context_entry.hi,
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@ -1121,7 +1124,7 @@ static void vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
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} else {
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vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write);
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}
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return;
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goto error;
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}
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/* Update context-cache */
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trace_vtd_iotlb_cc_update(bus_num, devfn, ce.hi, ce.lo,
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@ -1136,8 +1139,9 @@ static void vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
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* Also, let's ignore IOTLB caching as well for PT devices.
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*/
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if (vtd_ce_get_type(&ce) == VTD_CONTEXT_TT_PASS_THROUGH) {
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entry->iova = addr & VTD_PAGE_MASK;
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entry->translated_addr = entry->iova;
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entry->addr_mask = VTD_PAGE_SIZE - 1;
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entry->addr_mask = VTD_PAGE_MASK;
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entry->perm = IOMMU_RW;
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trace_vtd_translate_pt(source_id, entry->iova);
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@ -1152,7 +1156,7 @@ static void vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
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*/
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vtd_pt_enable_fast_path(s, source_id);
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return;
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return true;
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}
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ret_fr = vtd_iova_to_slpte(&ce, addr, is_write, &slpte, &level,
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@ -1164,7 +1168,7 @@ static void vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
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} else {
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vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write);
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}
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return;
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goto error;
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}
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page_mask = vtd_slpt_level_page_mask(level);
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@ -1175,6 +1179,14 @@ out:
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entry->translated_addr = vtd_get_slpte_addr(slpte) & page_mask;
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entry->addr_mask = ~page_mask;
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entry->perm = IOMMU_ACCESS_FLAG(reads, writes);
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return true;
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error:
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entry->iova = 0;
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entry->translated_addr = 0;
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entry->addr_mask = 0;
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entry->perm = IOMMU_NONE;
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return false;
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}
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static void vtd_root_table_setup(IntelIOMMUState *s)
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@ -2252,32 +2264,38 @@ static IOMMUTLBEntry vtd_iommu_translate(MemoryRegion *iommu, hwaddr addr,
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{
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VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu);
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IntelIOMMUState *s = vtd_as->iommu_state;
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IOMMUTLBEntry ret = {
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IOMMUTLBEntry iotlb = {
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/* We'll fill in the rest later. */
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.target_as = &address_space_memory,
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.iova = addr,
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.translated_addr = 0,
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.addr_mask = ~(hwaddr)0,
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.perm = IOMMU_NONE,
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};
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bool success;
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if (!s->dmar_enabled) {
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if (likely(s->dmar_enabled)) {
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success = vtd_do_iommu_translate(vtd_as, vtd_as->bus, vtd_as->devfn,
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addr, flag & IOMMU_WO, &iotlb);
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} else {
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/* DMAR disabled, passthrough, use 4k-page*/
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ret.iova = addr & VTD_PAGE_MASK_4K;
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ret.translated_addr = addr & VTD_PAGE_MASK_4K;
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ret.addr_mask = ~VTD_PAGE_MASK_4K;
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ret.perm = IOMMU_RW;
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return ret;
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iotlb.iova = addr & VTD_PAGE_MASK_4K;
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iotlb.translated_addr = addr & VTD_PAGE_MASK_4K;
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iotlb.addr_mask = ~VTD_PAGE_MASK_4K;
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iotlb.perm = IOMMU_RW;
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success = true;
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}
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vtd_do_iommu_translate(vtd_as, vtd_as->bus, vtd_as->devfn, addr,
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flag & IOMMU_WO, &ret);
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if (likely(success)) {
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trace_vtd_dmar_translate(pci_bus_num(vtd_as->bus),
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VTD_PCI_SLOT(vtd_as->devfn),
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VTD_PCI_FUNC(vtd_as->devfn),
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iotlb.iova, iotlb.translated_addr,
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iotlb.addr_mask);
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} else {
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trace_vtd_err_dmar_translate(pci_bus_num(vtd_as->bus),
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VTD_PCI_SLOT(vtd_as->devfn),
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VTD_PCI_FUNC(vtd_as->devfn),
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iotlb.iova);
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}
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trace_vtd_dmar_translate(pci_bus_num(vtd_as->bus),
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VTD_PCI_SLOT(vtd_as->devfn),
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VTD_PCI_FUNC(vtd_as->devfn),
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ret.iova, ret.translated_addr, ret.addr_mask);
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return ret;
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return iotlb;
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}
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static void vtd_iommu_notify_flag_changed(MemoryRegion *iommu,
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@ -384,6 +384,7 @@ typedef struct VTDIOTLBPageInvInfo VTDIOTLBPageInvInfo;
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/* Pagesize of VTD paging structures, including root and context tables */
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#define VTD_PAGE_SHIFT 12
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#define VTD_PAGE_SIZE (1ULL << VTD_PAGE_SHIFT)
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#define VTD_PAGE_MASK (VTD_PAGE_SIZE - 1)
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#define VTD_PAGE_SHIFT_4K 12
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#define VTD_PAGE_MASK_4K (~((1ULL << VTD_PAGE_SHIFT_4K) - 1))
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@ -73,6 +73,7 @@ vtd_err_dmar_iova_overflow(uint64_t iova) "iova 0x%"PRIx64
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vtd_err_dmar_slpte_read_error(uint64_t iova, int level) "iova 0x%"PRIx64" level %d"
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vtd_err_dmar_slpte_perm_error(uint64_t iova, int level, uint64_t slpte, bool is_write) "iova 0x%"PRIx64" level %d slpte 0x%"PRIx64" write %d"
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vtd_err_dmar_slpte_resv_error(uint64_t iova, int level, uint64_t slpte) "iova 0x%"PRIx64" level %d slpte 0x%"PRIx64
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vtd_err_dmar_translate(uint8_t bus, uint8_t slot, uint8_t func, uint64_t iova) "dev %02x:%02x.%02x iova 0x%"PRIx64
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vtd_err_qi_enable(uint16_t tail) "tail 0x%"PRIx16
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vtd_err_qi_disable(uint16_t head, uint16_t tail, int type) "head 0x%"PRIx16" tail 0x%"PRIx16" last_desc_type %d"
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vtd_err_qi_tail(uint16_t tail, uint16_t size) "tail 0x%"PRIx16" size 0x%"PRIx16
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