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tcg: Change flush_icache_range arguments to uintptr_t

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Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2013-08-20 14:22:50 -07:00
parent 35aa3fb387
commit b93949ef6a
10 changed files with 17 additions and 31 deletions
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3
tcg/aarch64/tcg-target.h
View file

@ -96,8 +96,7 @@ enum {
TCG_AREG0 = TCG_REG_X19,
};
static inline void flush_icache_range(tcg_target_ulong start,
tcg_target_ulong stop)
static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
{
__builtin___clear_cache((char *)start, (char *)stop);
}

9
tcg/arm/tcg-target.h
View file

@ -92,15 +92,14 @@ enum {
TCG_AREG0 = TCG_REG_R6,
};
static inline void flush_icache_range(tcg_target_ulong start,
tcg_target_ulong stop)
static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
{
#if QEMU_GNUC_PREREQ(4, 1)
__builtin___clear_cache((char *) start, (char *) stop);
#else
register unsigned long _beg __asm ("a1") = start;
register unsigned long _end __asm ("a2") = stop;
register unsigned long _flg __asm ("a3") = 0;
register uintptr_t _beg __asm("a1") = start;
register uintptr_t _end __asm("a2") = stop;
register uintptr_t _flg __asm("a3") = 0;
__asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
#endif
}

3
tcg/hppa/tcg-target.h
View file

@ -111,8 +111,7 @@ typedef enum {
#define TCG_AREG0 TCG_REG_R17
static inline void flush_icache_range(tcg_target_ulong start,
tcg_target_ulong stop)
static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
{
start &= ~31;
while (start <= stop) {

3
tcg/i386/tcg-target.h
View file

@ -139,8 +139,7 @@ typedef enum {
# define TCG_AREG0 TCG_REG_EBP
#endif
static inline void flush_icache_range(tcg_target_ulong start,
tcg_target_ulong stop)
static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
{
}

3
tcg/ia64/tcg-target.h
View file

@ -162,8 +162,7 @@ typedef enum {
#define TCG_AREG0 TCG_REG_R7
static inline void flush_icache_range(tcg_target_ulong start,
tcg_target_ulong stop)
static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
{
start = start & ~(32UL - 1UL);
stop = (stop + (32UL - 1UL)) & ~(32UL - 1UL);

3
tcg/mips/tcg-target.h
View file

@ -127,8 +127,7 @@ typedef enum {
#include <sys/cachectl.h>
#endif
static inline void flush_icache_range(tcg_target_ulong start,
tcg_target_ulong stop)
static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
{
cacheflush ((void *)start, stop-start, ICACHE);
}

3
tcg/s390/tcg-target.h
View file

@ -114,8 +114,7 @@ enum {
TCG_AREG0 = TCG_REG_R10,
};
static inline void flush_icache_range(tcg_target_ulong start,
tcg_target_ulong stop)
static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
{
}

12
tcg/sparc/tcg-target.h
View file

@ -142,16 +142,12 @@ typedef enum {
#define TCG_AREG0 TCG_REG_I0
static inline void flush_icache_range(tcg_target_ulong start,
tcg_target_ulong stop)
static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
{
unsigned long p;
p = start & ~(8UL - 1UL);
stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL);
for (; p < stop; p += 8)
uintptr_t p;
for (p = start & -8; p < (stop + 7) & -8; p += 8) {
__asm__ __volatile__("flush\t%0" : : "r" (p));
}
}
#endif

6
tcg/tcg.c
View file

@ -293,8 +293,7 @@ void tcg_prologue_init(TCGContext *s)
s->code_buf = s->code_gen_prologue;
s->code_ptr = s->code_buf;
tcg_target_qemu_prologue(s);
flush_icache_range((tcg_target_ulong)s->code_buf,
(tcg_target_ulong)s->code_ptr);
flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr);
#ifdef DEBUG_DISAS
if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) {
@ -2415,8 +2414,7 @@ int tcg_gen_code(TCGContext *s, uint8_t *gen_code_buf)
tcg_gen_code_common(s, gen_code_buf, -1);
/* flush instruction cache */
flush_icache_range((tcg_target_ulong)gen_code_buf,
(tcg_target_ulong)s->code_ptr);
flush_icache_range((uintptr_t)gen_code_buf, (uintptr_t)s->code_ptr);
return s->code_ptr - gen_code_buf;
}

3
tcg/tci/tcg-target.h
View file

@ -172,8 +172,7 @@ void tci_disas(uint8_t opc);
tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
#define tcg_qemu_tb_exec tcg_qemu_tb_exec
static inline void flush_icache_range(tcg_target_ulong start,
tcg_target_ulong stop)
static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
{
}