pl041: Rename pl041_state to PL041State
Reviewed-by: Hu Tao <hutao@cn.fujitsu.com> [AF: Split off renaming from QOM cast changes] Signed-off-by: Andreas Färber <afaerber@suse.de>
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@ -70,7 +70,7 @@ typedef struct {
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uint8_t rx_sample_size;
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uint8_t rx_sample_size;
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} pl041_channel;
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} pl041_channel;
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typedef struct {
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typedef struct PL041State {
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SysBusDevice busdev;
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SysBusDevice busdev;
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MemoryRegion iomem;
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MemoryRegion iomem;
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qemu_irq irq;
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qemu_irq irq;
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@ -80,7 +80,7 @@ typedef struct {
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pl041_regfile regs;
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pl041_regfile regs;
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pl041_channel fifo1;
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pl041_channel fifo1;
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lm4549_state codec;
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lm4549_state codec;
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} pl041_state;
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} PL041State;
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static const unsigned char pl041_default_id[8] = {
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static const unsigned char pl041_default_id[8] = {
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@ -107,7 +107,7 @@ static const char *get_reg_name(hwaddr offset)
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}
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}
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#endif
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#endif
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static uint8_t pl041_compute_periphid3(pl041_state *s)
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static uint8_t pl041_compute_periphid3(PL041State *s)
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{
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{
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uint8_t id3 = 1; /* One channel */
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uint8_t id3 = 1; /* One channel */
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@ -142,7 +142,7 @@ static uint8_t pl041_compute_periphid3(pl041_state *s)
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return id3;
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return id3;
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}
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}
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static void pl041_reset(pl041_state *s)
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static void pl041_reset(PL041State *s)
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{
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{
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DBG_L1("pl041_reset\n");
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DBG_L1("pl041_reset\n");
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@ -156,7 +156,7 @@ static void pl041_reset(pl041_state *s)
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}
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}
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static void pl041_fifo1_write(pl041_state *s, uint32_t value)
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static void pl041_fifo1_write(PL041State *s, uint32_t value)
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{
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{
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pl041_channel *channel = &s->fifo1;
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pl041_channel *channel = &s->fifo1;
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pl041_fifo *fifo = &s->fifo1.tx_fifo;
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pl041_fifo *fifo = &s->fifo1.tx_fifo;
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@ -239,7 +239,7 @@ static void pl041_fifo1_write(pl041_state *s, uint32_t value)
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DBG_L2("fifo1_push sr1 = 0x%08x\n", s->regs.sr1);
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DBG_L2("fifo1_push sr1 = 0x%08x\n", s->regs.sr1);
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}
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}
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static void pl041_fifo1_transmit(pl041_state *s)
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static void pl041_fifo1_transmit(PL041State *s)
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{
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{
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pl041_channel *channel = &s->fifo1;
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pl041_channel *channel = &s->fifo1;
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pl041_fifo *fifo = &s->fifo1.tx_fifo;
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pl041_fifo *fifo = &s->fifo1.tx_fifo;
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@ -291,7 +291,7 @@ static void pl041_fifo1_transmit(pl041_state *s)
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}
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}
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}
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}
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static void pl041_isr1_update(pl041_state *s)
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static void pl041_isr1_update(PL041State *s)
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{
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{
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/* Update ISR1 */
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/* Update ISR1 */
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if (s->regs.sr1 & TXUNDERRUN) {
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if (s->regs.sr1 & TXUNDERRUN) {
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@ -320,7 +320,7 @@ static void pl041_isr1_update(pl041_state *s)
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static void pl041_request_data(void *opaque)
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static void pl041_request_data(void *opaque)
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{
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{
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pl041_state *s = (pl041_state *)opaque;
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PL041State *s = (PL041State *)opaque;
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/* Trigger pending transfers */
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/* Trigger pending transfers */
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pl041_fifo1_transmit(s);
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pl041_fifo1_transmit(s);
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@ -330,7 +330,7 @@ static void pl041_request_data(void *opaque)
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static uint64_t pl041_read(void *opaque, hwaddr offset,
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static uint64_t pl041_read(void *opaque, hwaddr offset,
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unsigned size)
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unsigned size)
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{
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{
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pl041_state *s = (pl041_state *)opaque;
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PL041State *s = (PL041State *)opaque;
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int value;
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int value;
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if ((offset >= PL041_periphid0) && (offset <= PL041_pcellid3)) {
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if ((offset >= PL041_periphid0) && (offset <= PL041_pcellid3)) {
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@ -364,7 +364,7 @@ static uint64_t pl041_read(void *opaque, hwaddr offset,
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static void pl041_write(void *opaque, hwaddr offset,
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static void pl041_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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uint64_t value, unsigned size)
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{
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{
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pl041_state *s = (pl041_state *)opaque;
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PL041State *s = (PL041State *)opaque;
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uint16_t control, data;
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uint16_t control, data;
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uint32_t result;
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uint32_t result;
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@ -504,7 +504,7 @@ static void pl041_write(void *opaque, hwaddr offset,
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static void pl041_device_reset(DeviceState *d)
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static void pl041_device_reset(DeviceState *d)
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{
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{
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pl041_state *s = DO_UPCAST(pl041_state, busdev.qdev, d);
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PL041State *s = DO_UPCAST(PL041State, busdev.qdev, d);
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pl041_reset(s);
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pl041_reset(s);
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}
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}
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@ -517,7 +517,7 @@ static const MemoryRegionOps pl041_ops = {
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static int pl041_init(SysBusDevice *dev)
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static int pl041_init(SysBusDevice *dev)
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{
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{
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pl041_state *s = FROM_SYSBUS(pl041_state, dev);
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PL041State *s = FROM_SYSBUS(PL041State, dev);
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DBG_L1("pl041_init 0x%08x\n", (uint32_t)s);
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DBG_L1("pl041_init 0x%08x\n", (uint32_t)s);
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@ -603,12 +603,12 @@ static const VMStateDescription vmstate_pl041 = {
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.version_id = 1,
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(fifo_depth, pl041_state),
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VMSTATE_UINT32(fifo_depth, PL041State),
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VMSTATE_STRUCT(regs, pl041_state, 0,
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VMSTATE_STRUCT(regs, PL041State, 0,
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vmstate_pl041_regfile, pl041_regfile),
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vmstate_pl041_regfile, pl041_regfile),
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VMSTATE_STRUCT(fifo1, pl041_state, 0,
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VMSTATE_STRUCT(fifo1, PL041State, 0,
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vmstate_pl041_channel, pl041_channel),
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vmstate_pl041_channel, pl041_channel),
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VMSTATE_STRUCT(codec, pl041_state, 0,
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VMSTATE_STRUCT(codec, PL041State, 0,
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vmstate_lm4549_state, lm4549_state),
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vmstate_lm4549_state, lm4549_state),
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VMSTATE_END_OF_LIST()
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VMSTATE_END_OF_LIST()
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}
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}
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@ -616,7 +616,8 @@ static const VMStateDescription vmstate_pl041 = {
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static Property pl041_device_properties[] = {
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static Property pl041_device_properties[] = {
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/* Non-compact FIFO depth property */
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/* Non-compact FIFO depth property */
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DEFINE_PROP_UINT32("nc_fifo_depth", pl041_state, fifo_depth, DEFAULT_FIFO_DEPTH),
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DEFINE_PROP_UINT32("nc_fifo_depth", PL041State, fifo_depth,
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DEFAULT_FIFO_DEPTH),
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DEFINE_PROP_END_OF_LIST(),
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DEFINE_PROP_END_OF_LIST(),
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};
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};
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@ -636,7 +637,7 @@ static void pl041_device_class_init(ObjectClass *klass, void *data)
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static const TypeInfo pl041_device_info = {
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static const TypeInfo pl041_device_info = {
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.name = "pl041",
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.name = "pl041",
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.parent = TYPE_SYS_BUS_DEVICE,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(pl041_state),
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.instance_size = sizeof(PL041State),
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.class_init = pl041_device_class_init,
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.class_init = pl041_device_class_init,
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};
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};
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