target/arm: Hoist XSCALE_CPAR, VECLEN, VECSTRIDE in cpu_get_tb_cpu_state
We do not need to compute any of these values for M-profile. Further, XSCALE_CPAR overlaps VECSTRIDE so obviously the two sets must be mutually exclusive. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -11235,21 +11235,28 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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}
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} else {
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flags = rebuild_hflags_a32(env, fp_el, mmu_idx);
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/*
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* Note that XSCALE_CPAR shares bits with VECSTRIDE.
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* Note that VECLEN+VECSTRIDE are RES0 for M-profile.
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*/
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if (arm_feature(env, ARM_FEATURE_XSCALE)) {
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flags = FIELD_DP32(flags, TBFLAG_A32,
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XSCALE_CPAR, env->cp15.c15_cpar);
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} else {
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flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN,
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env->vfp.vec_len);
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flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE,
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env->vfp.vec_stride);
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}
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}
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flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb);
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flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len);
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flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride);
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flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits);
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if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)
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|| arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) {
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flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
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}
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/* Note that XSCALE_CPAR shares bits with VECSTRIDE */
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if (arm_feature(env, ARM_FEATURE_XSCALE)) {
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flags = FIELD_DP32(flags, TBFLAG_A32,
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XSCALE_CPAR, env->cp15.c15_cpar);
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}
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}
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/* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
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