target/riscv: hardwire bits in hideleg and hedeleg
The specification mandates for certain bits to be hardwired in the hypervisor delegation registers. This was not being enforced. Signed-off-by: Jose Martins <josemartins90@gmail.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210522155902.374439-1-josemartins90@gmail.com [ Changes by AF: - Improve indentation - Convert delegable_excps to a #define to avoid failures with GCC 8 ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -411,28 +411,36 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
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static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
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static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
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VS_MODE_INTERRUPTS;
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VS_MODE_INTERRUPTS;
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static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
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static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
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static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
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VS_MODE_INTERRUPTS;
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VS_MODE_INTERRUPTS;
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static const target_ulong delegable_excps =
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#define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
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(1ULL << (RISCV_EXCP_INST_ADDR_MIS)) |
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(1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
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(1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) |
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(1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
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(1ULL << (RISCV_EXCP_ILLEGAL_INST)) |
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(1ULL << (RISCV_EXCP_BREAKPOINT)) | \
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(1ULL << (RISCV_EXCP_BREAKPOINT)) |
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(1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \
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(1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) |
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(1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \
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(1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) |
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(1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \
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(1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) |
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(1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \
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(1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) |
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(1ULL << (RISCV_EXCP_U_ECALL)) | \
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(1ULL << (RISCV_EXCP_U_ECALL)) |
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(1ULL << (RISCV_EXCP_S_ECALL)) | \
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(1ULL << (RISCV_EXCP_S_ECALL)) |
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(1ULL << (RISCV_EXCP_VS_ECALL)) | \
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(1ULL << (RISCV_EXCP_M_ECALL)) | \
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(1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \
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(1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \
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(1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \
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(1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \
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(1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \
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(1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \
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(1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)))
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static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS &
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~((1ULL << (RISCV_EXCP_S_ECALL)) |
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(1ULL << (RISCV_EXCP_VS_ECALL)) |
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(1ULL << (RISCV_EXCP_VS_ECALL)) |
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(1ULL << (RISCV_EXCP_M_ECALL)) |
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(1ULL << (RISCV_EXCP_M_ECALL)) |
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(1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) |
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(1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) |
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(1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) |
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(1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
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(1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
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(1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
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(1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
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(1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
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(1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
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(1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
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(1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
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static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
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static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
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SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
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SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
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SSTATUS_SUM | SSTATUS_MXR;
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SSTATUS_SUM | SSTATUS_MXR;
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@ -620,7 +628,7 @@ static RISCVException read_medeleg(CPURISCVState *env, int csrno,
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static RISCVException write_medeleg(CPURISCVState *env, int csrno,
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static RISCVException write_medeleg(CPURISCVState *env, int csrno,
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target_ulong val)
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target_ulong val)
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{
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{
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env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps);
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env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS);
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return RISCV_EXCP_NONE;
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return RISCV_EXCP_NONE;
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}
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}
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@ -1039,7 +1047,7 @@ static RISCVException read_hedeleg(CPURISCVState *env, int csrno,
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static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
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static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
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target_ulong val)
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target_ulong val)
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{
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{
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env->hedeleg = val;
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env->hedeleg = val & vs_delegable_excps;
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return RISCV_EXCP_NONE;
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return RISCV_EXCP_NONE;
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}
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}
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@ -1053,7 +1061,7 @@ static RISCVException read_hideleg(CPURISCVState *env, int csrno,
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static RISCVException write_hideleg(CPURISCVState *env, int csrno,
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static RISCVException write_hideleg(CPURISCVState *env, int csrno,
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target_ulong val)
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target_ulong val)
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{
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{
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env->hideleg = val;
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env->hideleg = val & vs_delegable_ints;
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return RISCV_EXCP_NONE;
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return RISCV_EXCP_NONE;
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}
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}
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