e1000: Introduced an array to control the access to the MAC registers
The array of uint8_t's which is introduced here, contains access metadata about the MAC registers: if a register is accessible, but partly implemented, or if a register requires a certain compatibility flag in order to be accessed. Currently, 6 hypothetical flags are supported (3 exist for e1000 so far) but in the future, if more than 6 flags will be needed, the datatype of this array can simply be swapped for a larger one. This patch is intended to solve the following current problems: 1) In a scenario of migration between different versions of QEMU, which differ by the MAC registers implemented in them, some registers need not to be active if a compatibility flag is set, in order to preserve the machine's state perfectly for the older version. Checking this for each register individually, would create a lot of clutter in the code. 2) Some registers are (or may be) only partly implemented (e.g. placeholders that allow reading and writing, but lack other functions). In such cases it is better to print a debug warning on read/write attempts. As above, dealing with this functionality on a per-register level, would require longer and more messy code. Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com> Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
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@ -142,6 +142,8 @@ typedef struct E1000State_st {
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uint32_t compat_flags;
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} E1000State;
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#define chkflag(x) (s->compat_flags & E1000_FLAG_##x)
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typedef struct E1000BaseClass {
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PCIDeviceClass parent_class;
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uint16_t phy_id2;
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@ -195,8 +197,7 @@ e1000_link_up(E1000State *s)
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static bool
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have_autoneg(E1000State *s)
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{
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return (s->compat_flags & E1000_FLAG_AUTONEG) &&
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(s->phy_reg[PHY_CTRL] & MII_CR_AUTO_NEG_EN);
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return chkflag(AUTONEG) && (s->phy_reg[PHY_CTRL] & MII_CR_AUTO_NEG_EN);
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}
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static void
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@ -321,7 +322,7 @@ set_interrupt_cause(E1000State *s, int index, uint32_t val)
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if (s->mit_timer_on) {
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return;
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}
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if (s->compat_flags & E1000_FLAG_MIT) {
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if (chkflag(MIT)) {
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/* Compute the next mitigation delay according to pending
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* interrupts and the current values of RADV (provided
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* RDTR!=0), TADV and ITR.
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@ -1258,6 +1259,18 @@ static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
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enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
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enum { MAC_ACCESS_PARTIAL = 1, MAC_ACCESS_FLAG_NEEDED = 2 };
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#define markflag(x) ((E1000_FLAG_##x << 2) | MAC_ACCESS_FLAG_NEEDED)
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/* In the array below the meaning of the bits is: [f|f|f|f|f|f|n|p]
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* f - flag bits (up to 6 possible flags)
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* n - flag needed
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* p - partially implenented */
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static const uint8_t mac_reg_access[0x8000] = {
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[RDTR] = markflag(MIT), [TADV] = markflag(MIT),
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[RADV] = markflag(MIT), [ITR] = markflag(MIT),
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};
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static void
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e1000_mmio_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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@ -1266,9 +1279,20 @@ e1000_mmio_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned int index = (addr & 0x1ffff) >> 2;
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if (index < NWRITEOPS && macreg_writeops[index]) {
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macreg_writeops[index](s, index, val);
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if (!(mac_reg_access[index] & MAC_ACCESS_FLAG_NEEDED)
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|| (s->compat_flags & (mac_reg_access[index] >> 2))) {
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if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
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DBGOUT(GENERAL, "Writing to register at offset: 0x%08x. "
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"It is not fully implemented.\n", index<<2);
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}
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macreg_writeops[index](s, index, val);
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} else { /* "flag needed" bit is set, but the flag is not active */
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DBGOUT(MMIO, "MMIO write attempt to disabled reg. addr=0x%08x\n",
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index<<2);
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}
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} else if (index < NREADOPS && macreg_readops[index]) {
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DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04"PRIx64"\n", index<<2, val);
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DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04"PRIx64"\n",
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index<<2, val);
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} else {
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DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08"PRIx64"\n",
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index<<2, val);
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@ -1281,11 +1305,21 @@ e1000_mmio_read(void *opaque, hwaddr addr, unsigned size)
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E1000State *s = opaque;
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unsigned int index = (addr & 0x1ffff) >> 2;
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if (index < NREADOPS && macreg_readops[index])
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{
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return macreg_readops[index](s, index);
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if (index < NREADOPS && macreg_readops[index]) {
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if (!(mac_reg_access[index] & MAC_ACCESS_FLAG_NEEDED)
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|| (s->compat_flags & (mac_reg_access[index] >> 2))) {
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if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
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DBGOUT(GENERAL, "Reading register at offset: 0x%08x. "
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"It is not fully implemented.\n", index<<2);
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}
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return macreg_readops[index](s, index);
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} else { /* "flag needed" bit is set, but the flag is not active */
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DBGOUT(MMIO, "MMIO read attempt of disabled reg. addr=0x%08x\n",
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index<<2);
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}
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} else {
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DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
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}
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DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
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return 0;
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}
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@ -1352,7 +1386,7 @@ static int e1000_post_load(void *opaque, int version_id)
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E1000State *s = opaque;
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NetClientState *nc = qemu_get_queue(s->nic);
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if (!(s->compat_flags & E1000_FLAG_MIT)) {
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if (!chkflag(MIT)) {
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s->mac_reg[ITR] = s->mac_reg[RDTR] = s->mac_reg[RADV] =
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s->mac_reg[TADV] = 0;
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s->mit_irq_level = false;
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@ -1379,14 +1413,14 @@ static bool e1000_mit_state_needed(void *opaque)
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{
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E1000State *s = opaque;
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return s->compat_flags & E1000_FLAG_MIT;
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return chkflag(MIT);
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}
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static bool e1000_full_mac_needed(void *opaque)
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{
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E1000State *s = opaque;
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return s->compat_flags & E1000_FLAG_MAC;
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return chkflag(MAC);
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}
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static const VMStateDescription vmstate_e1000_mit_state = {
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