macio: move unaligned DMA write code into separate pmac_dma_write() function
Similarly switch the macio IDE routines over to use the new function and tidy-up the remaining code as required. [Maintainer edit: printf format codes adjusted for 32/64bit. --js] Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: John Snow <jsnow@redhat.com> Message-id: 1425939893-14404-3-git-send-email-mark.cave-ayland@ilande.co.uk Signed-off-by: John Snow <jsnow@redhat.com>
This commit is contained in:
Mark Cave-Ayland
John Snow
parent
4827ac1e8f
commit
bd4214fc92
270
hw/ide/macio.c
270
hw/ide/macio.c
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@ -144,6 +144,101 @@ static void pmac_dma_read(BlockBackend *blk,
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m->aiocb = blk_aio_readv(blk, sector_num, &io->iov, nsector, cb, io);
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}
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static void pmac_dma_write(BlockBackend *blk,
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int64_t sector_num, int nb_sectors,
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void (*cb)(void *opaque, int ret), void *opaque)
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{
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DBDMA_io *io = opaque;
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MACIOIDEState *m = io->opaque;
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IDEState *s = idebus_active_if(&m->bus);
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dma_addr_t dma_addr, dma_len;
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void *mem;
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int nsector, remainder;
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int extra = 0;
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qemu_iovec_destroy(&io->iov);
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qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
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if (io->remainder_len > 0) {
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/* Return remainder of request */
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int transfer = MIN(io->remainder_len, io->len);
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MACIO_DPRINTF("--- processing write remainder %x\n", transfer);
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cpu_physical_memory_read(io->addr,
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&io->remainder + (0x200 - transfer),
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transfer);
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io->remainder_len -= transfer;
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io->len -= transfer;
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io->addr += transfer;
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s->io_buffer_index += transfer;
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s->io_buffer_size -= transfer;
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if (io->remainder_len != 0) {
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/* Still waiting for remainder */
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return;
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}
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MACIO_DPRINTF("--> prepending bounce buffer with size 0x200\n");
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/* Sector transfer complete - prepend to request */
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qemu_iovec_add(&io->iov, &io->remainder, 0x200);
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extra = 1;
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}
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if (s->drive_kind == IDE_CD) {
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sector_num = (int64_t)(s->lba << 2) + (s->io_buffer_index >> 9);
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} else {
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sector_num = ide_get_sector(s) + (s->io_buffer_index >> 9);
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}
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nsector = (io->len >> 9);
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remainder = io->len - (nsector << 9);
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MACIO_DPRINTF("--- DMA write transfer - addr: %" HWADDR_PRIx " len: %x\n",
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io->addr, io->len);
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MACIO_DPRINTF("xxx remainder: %x\n", remainder);
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MACIO_DPRINTF("xxx sector_num: %"PRIx64" nsector: %x\n",
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sector_num, nsector);
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dma_addr = io->addr;
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dma_len = io->len;
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mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
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DMA_DIRECTION_TO_DEVICE);
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if (!remainder) {
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MACIO_DPRINTF("--- DMA write aligned - addr: %" HWADDR_PRIx
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" len: %x\n", io->addr, io->len);
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qemu_iovec_add(&io->iov, mem, io->len);
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} else {
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/* Write up to last complete sector */
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MACIO_DPRINTF("--- DMA write unaligned - addr: %" HWADDR_PRIx
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" len: %x\n", io->addr, (nsector << 9));
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qemu_iovec_add(&io->iov, mem, (nsector << 9));
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MACIO_DPRINTF("--- DMA write read - bounce addr: %p "
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"remainder_len: %x\n", &io->remainder, remainder);
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cpu_physical_memory_read(io->addr + (nsector << 9), &io->remainder,
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remainder);
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io->remainder_len = 0x200 - remainder;
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MACIO_DPRINTF("xxx remainder_len: %x\n", io->remainder_len);
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}
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s->io_buffer_size -= ((nsector + extra) << 9);
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s->io_buffer_index += ((nsector + extra) << 9);
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io->len = 0;
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MACIO_DPRINTF("--- Block write transfer - sector_num: %"PRIx64" "
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"nsector: %x\n", sector_num, nsector + extra);
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m->aiocb = blk_aio_writev(blk, sector_num, &io->iov, nsector + extra, cb,
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io);
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}
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static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
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{
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DBDMA_io *io = opaque;
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@ -218,24 +313,19 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
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DBDMA_io *io = opaque;
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MACIOIDEState *m = io->opaque;
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IDEState *s = idebus_active_if(&m->bus);
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int n = 0;
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int64_t sector_num;
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int unaligned;
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int nsector, remainder;
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MACIO_DPRINTF("pmac_ide_transfer_cb\n");
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if (ret < 0) {
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MACIO_DPRINTF("DMA error\n");
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m->aiocb = NULL;
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qemu_sglist_destroy(&s->sg);
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ide_dma_error(s);
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io->remainder_len = 0;
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goto done;
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}
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if (--io->requests) {
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/* More requests still in flight */
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return;
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}
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if (!m->dma_active) {
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MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
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s->nsector, io->len, s->status);
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@ -244,155 +334,48 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
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return;
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}
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sector_num = ide_get_sector(s);
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MACIO_DPRINTF("io_buffer_size = %#x\n", s->io_buffer_size);
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if (s->io_buffer_size > 0) {
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m->aiocb = NULL;
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qemu_sglist_destroy(&s->sg);
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n = (s->io_buffer_size + 0x1ff) >> 9;
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sector_num += n;
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ide_set_sector(s, sector_num);
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s->nsector -= n;
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}
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if (io->finish_remain_read) {
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/* Finish a stale read from the last iteration */
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io->finish_remain_read = false;
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cpu_physical_memory_write(io->finish_addr, io->remainder,
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io->finish_len);
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}
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MACIO_DPRINTF("remainder: %d io->len: %d nsector: %d "
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"sector_num: %" PRId64 "\n",
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io->remainder_len, io->len, s->nsector, sector_num);
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if (io->remainder_len && io->len) {
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/* guest wants the rest of its previous transfer */
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int remainder_len = MIN(io->remainder_len, io->len);
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uint8_t *p = &io->remainder[0x200 - remainder_len];
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MACIO_DPRINTF("copying remainder %d bytes at %#" HWADDR_PRIx "\n",
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remainder_len, io->addr);
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switch (s->dma_cmd) {
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case IDE_DMA_READ:
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cpu_physical_memory_write(io->addr, p, remainder_len);
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break;
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case IDE_DMA_WRITE:
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cpu_physical_memory_read(io->addr, p, remainder_len);
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break;
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case IDE_DMA_TRIM:
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break;
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}
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io->addr += remainder_len;
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io->len -= remainder_len;
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io->remainder_len -= remainder_len;
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if (s->dma_cmd == IDE_DMA_WRITE && !io->remainder_len) {
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io->requests++;
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qemu_iovec_reset(&io->iov);
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qemu_iovec_add(&io->iov, io->remainder, 0x200);
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m->aiocb = blk_aio_writev(s->blk, sector_num - 1, &io->iov, 1,
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pmac_ide_transfer_cb, io);
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}
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}
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if (s->nsector == 0 && !io->remainder_len) {
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if (s->io_buffer_size <= 0) {
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MACIO_DPRINTF("end of transfer\n");
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s->status = READY_STAT | SEEK_STAT;
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ide_set_irq(s->bus);
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m->dma_active = false;
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}
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if (io->len == 0) {
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MACIO_DPRINTF("end of DMA\n");
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goto done;
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}
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/* launch next transfer */
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s->io_buffer_index = 0;
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s->io_buffer_size = MIN(io->len, s->nsector * 512);
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/* handle unaligned accesses first, get them over with and only do the
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remaining bulk transfer using our async DMA helpers */
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unaligned = io->len & 0x1ff;
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if (unaligned) {
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int nsector = io->len >> 9;
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MACIO_DPRINTF("precopying unaligned %d bytes to %#" HWADDR_PRIx "\n",
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unaligned, io->addr + io->len - unaligned);
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switch (s->dma_cmd) {
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case IDE_DMA_READ:
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io->requests++;
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io->finish_addr = io->addr + io->len - unaligned;
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io->finish_len = unaligned;
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io->finish_remain_read = true;
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qemu_iovec_reset(&io->iov);
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qemu_iovec_add(&io->iov, io->remainder, 0x200);
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m->aiocb = blk_aio_readv(s->blk, sector_num + nsector, &io->iov, 1,
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pmac_ide_transfer_cb, io);
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break;
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case IDE_DMA_WRITE:
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/* cache the contents in our io struct */
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cpu_physical_memory_read(io->addr + io->len - unaligned,
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io->remainder + io->remainder_len,
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unaligned);
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break;
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case IDE_DMA_TRIM:
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break;
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}
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if (io->len == 0) {
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MACIO_DPRINTF("End of DMA transfer\n");
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goto done;
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}
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MACIO_DPRINTF("io->len = %#x\n", io->len);
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/* Calculate number of sectors */
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sector_num = ide_get_sector(s) + (s->io_buffer_index >> 9);
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nsector = (io->len + 0x1ff) >> 9;
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remainder = io->len & 0x1ff;
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qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
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&address_space_memory);
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qemu_sglist_add(&s->sg, io->addr, io->len);
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io->addr += io->len + unaligned;
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io->remainder_len = (0x200 - unaligned) & 0x1ff;
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MACIO_DPRINTF("set remainder to: %d\n", io->remainder_len);
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s->nsector -= nsector;
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/* Only subsector reads happening */
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if (!io->len) {
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if (!io->requests) {
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io->requests++;
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pmac_ide_transfer_cb(opaque, ret);
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}
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return;
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}
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io->len = 0;
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MACIO_DPRINTF("sector_num=%" PRId64 " n=%d, nsector=%d, cmd_cmd=%d\n",
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sector_num, n, s->nsector, s->dma_cmd);
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MACIO_DPRINTF("nsector: %d remainder: %x\n", nsector, remainder);
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MACIO_DPRINTF("sector: %"PRIx64" %x\n", sector_num, nsector);
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switch (s->dma_cmd) {
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case IDE_DMA_READ:
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m->aiocb = dma_blk_read(s->blk, &s->sg, sector_num,
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pmac_ide_transfer_cb, io);
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pmac_dma_read(s->blk, sector_num, nsector, pmac_ide_transfer_cb, io);
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break;
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case IDE_DMA_WRITE:
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m->aiocb = dma_blk_write(s->blk, &s->sg, sector_num,
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pmac_ide_transfer_cb, io);
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pmac_dma_write(s->blk, sector_num, nsector, pmac_ide_transfer_cb, io);
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break;
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case IDE_DMA_TRIM:
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m->aiocb = dma_blk_io(s->blk, &s->sg, sector_num,
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ide_issue_trim, pmac_ide_transfer_cb, io,
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DMA_DIRECTION_TO_DEVICE);
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MACIO_DPRINTF("TRIM command issued!");
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break;
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}
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io->requests++;
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return;
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done:
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if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
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block_acct_done(blk_get_stats(s->blk), &s->acct);
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}
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io->dma_end(io);
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io->dma_end(opaque);
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}
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static void pmac_ide_transfer(DBDMA_io *io)
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@ -408,8 +391,6 @@ static void pmac_ide_transfer(DBDMA_io *io)
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pmac_ide_atapi_transfer_cb(io, 0);
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return;
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} else {
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s->io_buffer_size = 0;
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}
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switch (s->dma_cmd) {
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@ -425,7 +406,6 @@ static void pmac_ide_transfer(DBDMA_io *io)
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break;
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}
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io->requests++;
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pmac_ide_transfer_cb(io, 0);
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}
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@ -585,22 +565,24 @@ static void ide_dbdma_start(IDEDMA *dma, IDEState *s,
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DBDMA_io *io;
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int i;
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s->io_buffer_index = 0;
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if (s->drive_kind == IDE_CD) {
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s->io_buffer_index = 0;
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s->io_buffer_size = s->packet_transfer_size;
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} else {
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s->io_buffer_size = s->nsector * 0x200;
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}
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MACIO_DPRINTF("\n\n------------ IDE transfer\n");
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MACIO_DPRINTF("buffer_size: %x buffer_index: %x\n",
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s->io_buffer_size, s->io_buffer_index);
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MACIO_DPRINTF("lba: %x size: %x\n", s->lba, s->io_buffer_size);
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MACIO_DPRINTF("-------------------------\n");
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MACIO_DPRINTF("\n\n------------ IDE transfer\n");
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MACIO_DPRINTF("buffer_size: %x buffer_index: %x\n",
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s->io_buffer_size, s->io_buffer_index);
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MACIO_DPRINTF("lba: %x size: %x\n", s->lba, s->io_buffer_size);
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MACIO_DPRINTF("-------------------------\n");
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for (i = 0; i < DBDMA_CHANNELS; i++) {
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io = &dbdma->channels[i].io;
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for (i = 0; i < DBDMA_CHANNELS; i++) {
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io = &dbdma->channels[i].io;
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if (io->opaque == m) {
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io->remainder_len = 0;
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}
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if (io->opaque == m) {
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io->remainder_len = 0;
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}
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}
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@ -43,10 +43,6 @@ struct DBDMA_io {
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uint8_t remainder[0x200];
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int remainder_len;
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QEMUIOVector iov;
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bool finish_remain_read;
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hwaddr finish_addr;
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hwaddr finish_len;
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int requests;
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};
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/*
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